As in the subject it just doesn't work. I think it's dir 1703 fault. It behaves very strange. With no SPDIF input attached BRATE0,1 seems to see 96kHz ( should be 48kHz ) and it doesn't change with 44.1 SPDIF input. Maybe there's something wrong with my circut??
Funny thing... Now dir1703 see right 48kHz, but then I plug CD-Rom wire ( just plug, not play ) it changes to 98kHz. 🙁
No one would help me?? I know that some of you have already built something with that chip and can share their experience. Inmy case seems that dir1703 can't lock the incoming SPDIF. Why? Maybe there is a mistake in the schematic??
Well my DIR works in a really odd way too. It will only work with a 48khz signal and wont auto lock onto anything else, even though it is set up to auto detect. I would appreciate it if someone would say all the conditions the DIR must be under to actually autodetect the sample frequency.
I've read that the input chip schould be 74HCU04, cos that's unbuffered version. I've got 74HC04 so far. Maybe that's the problem. I'll try with HCU then I have one.
kafka said:
No it doesnt...
Your only supplying the DIR1703 with a clock... you dont need to since it has its own clock generator.
The PLL1700 is unneeded.
Have a look at the schematic for my last DAC:
http://www.overclockers.com.au/~mwp/dac3/mwp-dac3-sch.pdf
The PLL1700 is only really needed when you need an easily changed rate clock source for multiple components.
MWP said:
Yes... but I've attached only a part of a whole schematic with pcm1804 and dit4096. The truth is that so far nothing works 🙁
!@$!#$#%@!#$%@#%&%&$^$ 
It was all the PLL1700 fault !! It works without it. Now I'm going to force PLL to work properly.
It was all the PLL1700 fault !! It works without it. Now I'm going to force PLL to work properly.PLL1700
Hi Kafka,
I designed a similar system to the one you are discribing. BTW Check the TI site for the newer version of the PLL1700 clock gen device.
The reason to use this over connecting the SCK out from the DIR straight into the SCK in on the DAC is this limits you to only using the default oversampling rate.
Sourcing all local clocks from a centralised clock point improves jitter performance considerably. It also provides flexibility with oversampling rates, and allows the designer to maximise the performance of the system.
Good luck with it
apollyon25
Hi Kafka,
I designed a similar system to the one you are discribing. BTW Check the TI site for the newer version of the PLL1700 clock gen device.
The reason to use this over connecting the SCK out from the DIR straight into the SCK in on the DAC is this limits you to only using the default oversampling rate.
Sourcing all local clocks from a centralised clock point improves jitter performance considerably. It also provides flexibility with oversampling rates, and allows the designer to maximise the performance of the system.
Good luck with it
apollyon25
All that work just to find out that the PLL1700 was broken. I've replaced it and the DAC works well... almost... one channel is louder then another. Resistors in the analog stage are matched to 0.1%. Where can I search for the mistake?
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