Hello friends,
I have acquired two AD1865K, and I'm researching my options on how to use them. My plan is to get the digital side done,m and then play with analog options. So the idea looks like this:
I have acquired two AD1865K, and I'm researching my options on how to use them. My plan is to get the digital side done,m and then play with analog options. So the idea looks like this:
- USB to I2S interface
- SRC4392 as a DIR, selector, and ASRC
- DF1704 as a digital filter and I2S to AD1865 compatible signal converter
- I think that DF1704 with output format set to 18 bits will drive the AD1865 inputs correctly, is that right?
- I need to set the SRC4392 output sampling rate to 96kHz (or 88,2kHz), to maintain compatibility with DF1704
- Can someone point me to a source about aliasing and how it is filtered in the digital and analog domains? I understand that it is very important, but not much more.
- Are those chips going to work in a configuration like this?
Thanks a lot folks.
Without studying the AD1865k and DF1704 datasheets, its hard to say if they are compatible or not. Have you attempted to do that yet?
Regarding SRC4392, its a great ASRC but you don't need it for asynchronous USB, and you would likely be better off remaining synchronous at the dac end if at all possible. If you can do that then the main use for SRC4392 would be to resample SPDIF or TOSLINK inputs so that the dac chip can reference to a local high-quality, low-jitter clock as the dac chip time standard.
Other than the chip stuff you have asked about, Vref for a dac is always one of the most important analog engineering problems to solve. It is the voltage reference standard for the dac. An off-the-shelf voltage regulator may measure well in PSS FFT tests, but not necessarily sound all that great when reproducing music with more dramatic dynamics.
Both time and voltage references are critical to ultimate dac performance. Then there is the output stage. Depending on the dac chip internals there may be some options for output stage design that might be optimized for different purposes. Best perceptual SQ and best PSS FFT measurements may or may not end up giving equal results. Depends.
Regarding SRC4392, its a great ASRC but you don't need it for asynchronous USB, and you would likely be better off remaining synchronous at the dac end if at all possible. If you can do that then the main use for SRC4392 would be to resample SPDIF or TOSLINK inputs so that the dac chip can reference to a local high-quality, low-jitter clock as the dac chip time standard.
Other than the chip stuff you have asked about, Vref for a dac is always one of the most important analog engineering problems to solve. It is the voltage reference standard for the dac. An off-the-shelf voltage regulator may measure well in PSS FFT tests, but not necessarily sound all that great when reproducing music with more dramatic dynamics.
Both time and voltage references are critical to ultimate dac performance. Then there is the output stage. Depending on the dac chip internals there may be some options for output stage design that might be optimized for different purposes. Best perceptual SQ and best PSS FFT measurements may or may not end up giving equal results. Depends.
Thank you for your post @Markw4
1. I have went through the datasheet, and it seems to me they are compatible.
The AD1865 is a DAC, just that. Its input is something that I have seen called: a digital filter interface.
Correct me if I'm wrong:
DataL/DataR - self-explanatory, each channel has its own data line
LatchL/LatchR - clock signal telling DAC that the data for the targeted channel is being transmitted. The data is written to the DAC when the latch input sees a falling edge.
BCK - base clock of the DAC, base for timings in communitaction.
The AD1865 writes the received data to the DAC on a falling edge on the Latch input. The DF1704 ends its transmission by a falling edge on the WCKO line. I would have to connect WCKO to both Latch inputs of the AD1865.
So far so good.
I want to use the SRC4392 to ensure the compatibility with all incoming signals (eg. USB Audio at 192kHz, getting downsampled to 96kHz) and to keep the sampling frequency high that will help with filtering in analogue stage. Push the Fs high, so I can use shallower filters. As you have mentioned it will also supply a high quality clock for the system.
You are right about the Vref and analog stage. They are vital to the sound of the DAC. Couldn't agree more with your experience.
That's why I'm planning to do this project in two stages: one that works, and one that sounds.
1. I have went through the datasheet, and it seems to me they are compatible.
The AD1865 is a DAC, just that. Its input is something that I have seen called: a digital filter interface.
Correct me if I'm wrong:
DataL/DataR - self-explanatory, each channel has its own data line
LatchL/LatchR - clock signal telling DAC that the data for the targeted channel is being transmitted. The data is written to the DAC when the latch input sees a falling edge.
BCK - base clock of the DAC, base for timings in communitaction.
The AD1865 writes the received data to the DAC on a falling edge on the Latch input. The DF1704 ends its transmission by a falling edge on the WCKO line. I would have to connect WCKO to both Latch inputs of the AD1865.
So far so good.
I want to use the SRC4392 to ensure the compatibility with all incoming signals (eg. USB Audio at 192kHz, getting downsampled to 96kHz) and to keep the sampling frequency high that will help with filtering in analogue stage. Push the Fs high, so I can use shallower filters. As you have mentioned it will also supply a high quality clock for the system.
You are right about the Vref and analog stage. They are vital to the sound of the DAC. Couldn't agree more with your experience.
That's why I'm planning to do this project in two stages: one that works, and one that sounds.
Okay. Guess I would say that ASRC is never as desirable as synchronous SRC when the latter is possible. Thus it is always better for SQ to do SRC in high quality software if using 'asynchronous USB' (i.e. a synchronous dac clock system which is asynchronous with the computer's clock). OTOH if using SPDF or TOSLINK then an ASRC may be the best choice if minimizing processing latency is paramount (e.g. sound for video needs to stay in sync). If no big concern about latency then FIFO buffering almost always beats ASRC since the former is bit perfect (so long as no FIFO overruns or underruns, that is).
Also, SRC4392 is not a good clock source. It can derive a MCLK signal from incoming digital audio, but its going to be more jittery than if SRC4392 is referenced to a separate high quality quartz crystal clock. In a higher performance dac a good crystal clock is used as the ASRC time reference and also to clock the dac chip itself.
Also, SRC4392 is not a good clock source. It can derive a MCLK signal from incoming digital audio, but its going to be more jittery than if SRC4392 is referenced to a separate high quality quartz crystal clock. In a higher performance dac a good crystal clock is used as the ASRC time reference and also to clock the dac chip itself.
I would prefer to use Roon's SRC, as I also think that it is better than any on-the-chip solution, but I want the DAC to be compatible with other digital sources. So that's why SRC4392 is doing the OS.
FIFO is way outside my current skills and comprehension, but I know about that solution.
SRC4392 provides a good-quality clock - my mistake. I meant SRC4392 with a high-quality clock generator.
I have created the symbols for the DF1704 and AD1865 in KiCAD, so I'm hoping to get the schematics done by the end of the weekend. Hopefully. I think it's going to be easier to discuss the topic then.
Thank you for helping me @Markw4
FIFO is way outside my current skills and comprehension, but I know about that solution.
SRC4392 provides a good-quality clock - my mistake. I meant SRC4392 with a high-quality clock generator.
I have created the symbols for the DF1704 and AD1865 in KiCAD, so I'm hoping to get the schematics done by the end of the weekend. Hopefully. I think it's going to be easier to discuss the topic then.
Thank you for helping me @Markw4
Based on many listening opinions, it is better to not use digital filter with AD1865 (make it without digital filter and NOS), or use better digital filter (like the HDCD PMD-200 or rare PMD-100). DF1704 has not very good reputation.
jitter in MCLK or BCK means nothing for the AD1865, the sound depends on the clean LE (LRCK, Latch).
jitter in MCLK or BCK means nothing for the AD1865, the sound depends on the clean LE (LRCK, Latch).
If the DF1704 is not good enough, you can use the SRC4392 to interpolate to 200 kHz or so and round it to 18 bits with dithering. You will then need some glue logic to interface its I2S output to the DAC chips. I think I designed such an interface some time ago, I can look it up.
Edit: see the attachment. I tried to keep the amount of data-related interference to the bare minimum and accepted half a sample of delay between left and right for that (at 200 kHz sample rate equivalent to the propagation time of sound through 0.85 mm of air). I designed it for someone from a Dutch audio forum who built and tested it, up to and including 192 kHz sample rate (although at 192 kHz and above, when the bit clock is 64 times the word clock, the clock duty cycle has to be better than the 35 %...65 % specified in the I2S standard to meet the AD1865 30 ns minimum pulse width requirement).
Edit: see the attachment. I tried to keep the amount of data-related interference to the bare minimum and accepted half a sample of delay between left and right for that (at 200 kHz sample rate equivalent to the propagation time of sound through 0.85 mm of air). I designed it for someone from a Dutch audio forum who built and tested it, up to and including 192 kHz sample rate (although at 192 kHz and above, when the bit clock is 64 times the word clock, the clock duty cycle has to be better than the 35 %...65 % specified in the I2S standard to meet the AD1865 30 ns minimum pulse width requirement).
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Thank you for your input 🙂 Are the PMD filters still available somewhere? I couldn't find it... I'm open to changing the setup, as long as I can buy genuine parts. Going NOS will require me to have very strong analogue filtering, right?
@MarcelvdG
Thank you for your advice. In my current understanding I need both digital, and analogue filtering to get rid of the aliasing, and switching noise of the DAC. If I leave out the digital filter, does that mean that I would need stronger analogue filtering?
The second part of your post implies that if I want to use Fs of 192kHz and above I would need a very clean signal clock, that will have a tighter spec than I2S standard?
Thank you for the schematics!
Is there any book, or articles that will help me get up to speed? They can be free or payed. I have grabbed a book about ADC/DAC but it is more of a guide, so it might not go deep enough for me. I'll see.
PMD100 or PMD200 are very rare these days and fetch ridiculous asking prices at ebay. I have PMD100 but I haven't compared it to other digital filters. It is limited to 44k1/48k and has only one filter but that has higher stopband attenuation (>120dB) than e.g. DF1704. More important feature may be the configurable deglitching period (i.e. stopped clock) which should work especially fine with AD1862 or AD1865.
@SomekPoland only used parts are available on ebay (genuine, but used) ... AD1862 or AD1865 don't need analog filtering, it's such a well made DAC 🙂
As far as I know, the more usual term for DACs is imaging, and aliasing for ADCs. Aliasing can lead to undesired frequency components in the audio band, imaging only to ultrasonic components, assuming that everything above half the sample rate is ultrasonic.
At 44.1 kHz sample rate, with no digital filter at all, you need a very steep analogue filter to pass 20 kHz content while suppressing images above 22.05 or 24.1 kHz (ideally you should suppress everything above 22.05 kHz, but DAC manufacturers almost always cheat).
However, the SRC4392 also contains digital filters. When you use it to convert everything to 200 kHz sample rate, the analogue filter can have a transition band to 100 kHz and becomes much more manageable.
Some audiophile NOS DACs hardly suppress images at all, their designers expect the ears of the listeners to do that for them. They only gradually roll off by 3.92 dB at half the sample rate and have notches at integer multiples of the sample rate. If cats or dogs have to listen to such DACs at sample rates below 176.4 kHz or 88.2 kHz, respectively, it's a form of animal abuse, because they do hear the images and they sound awful. (I once did an experiment where I simulated the sound of such a DAC at an 11.025 kHz sample rate, to make the images audible for a mere human.)
Not quite. The clock duty cycle requirements in the I2S standard are very relaxed, most crystal oscillators are far better. The spectral purity is not specified at all in the standard.
The I2S standard, AD1865 datasheet and a general article about digital audio in Linear Audio come to mind, I'll see if I can find links.
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@MarcelvdG
I have found the article about digital interpolation from the Linear Audio. It helped me a a bit to understand the topic.
The output of the SRC4392 will be:
Assuming Fs of 192kHz and 18bit word it looks like this:
We need to deliver two samples of 18 bits (36 bits in total), 192 000 times a second.
18 (bits) x 2(channels) x 192kHz = 6,912 MHz
The WS will be 384kHz as we need to fit two channels for each sample.
Your circuit doesn't change the SCK/BCK, so that's what the AD will receive. A period of 6,912 MHz is 14.467 uS so we should be in the green.
What feels off is that you have mentioned 30ns, and I know that was not without a reason. My result is multiple times bigger. Is my math off? Or have I misunderstood the problem?
I have found the article about digital interpolation from the Linear Audio. It helped me a a bit to understand the topic.
So not only will it make the analog stage easier to manage, but it will also eliminate the need for DF1704. Sounds like a good deal. Especially since you have kindly provided the logic converter.
The duty cycle of oscillators and generators. Has to provide a minimum of 30ns pulse for the AD1865.
The output of the SRC4392 will be:
Assuming Fs of 192kHz and 18bit word it looks like this:
We need to deliver two samples of 18 bits (36 bits in total), 192 000 times a second.
18 (bits) x 2(channels) x 192kHz = 6,912 MHz
The WS will be 384kHz as we need to fit two channels for each sample.
Your circuit doesn't change the SCK/BCK, so that's what the AD will receive. A period of 6,912 MHz is 14.467 uS so we should be in the green.
What feels off is that you have mentioned 30ns, and I know that was not without a reason. My result is multiple times bigger. Is my math off? Or have I misunderstood the problem?
The word select frequency is only 1 time the sample rate. Basically one channel is transported when WS is high and the other when it is low, except for the last bit.
When you look at page 25 of the SRC4392 datasheet, https://www.ti.com/product/SRC4392 , you will see that the bit clock is always 64 times the sample rate when you use the serial audio interfaces in master mode. That is, you either need to supply the clocks for the I2S output from external clock dividers and configure it in slave mode, or make sure you can handle a bit clock of 64 times the sample rate.
One thing I overlooked is that when the SRC4392 is used in master mode and hence generates the bit clock, it does so by dividing its master clock by an even number. Normally dividers by an even number produce near perfect 50 % duty cycles, so the whole discussion about duty cycles is unnecessary.
When you look at page 25 of the SRC4392 datasheet, https://www.ti.com/product/SRC4392 , you will see that the bit clock is always 64 times the sample rate when you use the serial audio interfaces in master mode. That is, you either need to supply the clocks for the I2S output from external clock dividers and configure it in slave mode, or make sure you can handle a bit clock of 64 times the sample rate.
One thing I overlooked is that when the SRC4392 is used in master mode and hence generates the bit clock, it does so by dividing its master clock by an even number. Normally dividers by an even number produce near perfect 50 % duty cycles, so the whole discussion about duty cycles is unnecessary.
I'm sorry, I haven't considered looking into the SRC4392 datasheet yet. I focused on I2S paper and AD1865 datasheet up until now.
With BCK = 64 x Fs, we get BCK = 12,288MHz and a period of 81,38ns. The pulse width is half of the period, so 40,7ns. Close one.
Because it has two states in one period, of course. Silly me.
I'm studying your article on Valve DAC. Hopefully, it will give me some additional insight into the matter. I'll go through the SRC datasheet and come back tomorrow.
Thank you very much, I greatly appreciate your help and time!
I'm glad you find my valve DAC article useful, but I actually meant another Linear Audio article, one that just explains the basics of digital audio, how oversampling and digital filtering reduce analogue reconstruction filtering requirements, what zero order hold filtering is, that sort of thing (I don't remember the name of the author or the title, but I'll find it when I go through my stack of Linear Audios). Then again, maybe all of that is already covered in the book about ADCs and DACs that you are reading.
Richard Lyons, "How discrete signal interpolation improves digital-to-analog conversion", Linear Audio volume 3, April 2012, pages 7...16
When you have a clock that only just meets the 35 % to 65 % duty cycle requirement from the I2S standard, the pulse width is only 35 % of 81.38 ns. Hence the need for a better duty cycle (which you get automatically when you divide a higher master clock frequency by two).