I did miss something...
and need to correct myself. Seem like I'm getting dyslectic.
Please ignore the first post, I have been warned about the "4040" ... - the 4046 I have not tried.
Arne K
Cobra2 said:
and need to correct myself. Seem like I'm getting dyslectic.
Please ignore the first post, I have been warned about the "4040" ... - the 4046 I have not tried.
Arne K
darkfenriz said:
Hi
I am having a bit of difficulty to understand your architecture. For some reason you avoid the use of CS8412, replace it with a complicated circuit that I doubt will work, followed by a phase comparator with integrated VCO of which everyone knows that the jitter performance is far from top class, and might even be on par with that of the 8412.
Could you eleborate on your design choices ?
best
Guido Tent said:
I will still need to use cs8412 or similar to get recovered data for a DAC.
I would like to have an ability to switch between clocks, the one recovered by 8412 (the 'acceptable' one) and the crappy one for some presentation of how jitter affects sound quality.
This also would be educational for me to design a clock recovery circuit from scratch I believe.
This is contrary to your design, where you are applying a narrow band PLL over a cs841x-recovered clock to get an ultra-low jitter of clock signal.
If I don't succeed in building a whole clock recovery circuit by myself, then I can switch between two different PLL loop filters of cs8412, like 1kohm and 47nF recomended in datasheet and 1k-100pF filter.
This also will give me two different jitter-rejection characteristics.
Am I right?
best regards
Adam
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