Digital newbie looking for good info:
So I have 11.xxMHz transport, a CS8412 and PCM63 dac and I'd like to create a zero-oversampling dac. The schematic for this is here:
http://www.diyaudio.com/forums/digital-source/65948-cs8412-pcm63-non-oversampling-3.html#post1598951
I can solder the thing together and it will probably work, but I'd like to understand how the various bits fit together, how the timings work etc.
Any help would be much appreciated!
So I have 11.xxMHz transport, a CS8412 and PCM63 dac and I'd like to create a zero-oversampling dac. The schematic for this is here:
http://www.diyaudio.com/forums/digital-source/65948-cs8412-pcm63-non-oversampling-3.html#post1598951
I can solder the thing together and it will probably work, but I'd like to understand how the various bits fit together, how the timings work etc.
Any help would be much appreciated!
So question 1:
The SPDIF is received by the CS8412, which then generates a clock and data output.
How do you determine what the clock should be for a given DAC?
How do you know if it should be 256*Fs or 384*Fs, where Fs is 44.1kHz?
The SPDIF is received by the CS8412, which then generates a clock and data output.
How do you determine what the clock should be for a given DAC?
How do you know if it should be 256*Fs or 384*Fs, where Fs is 44.1kHz?
The CS8412 produces a clock at 256*fs, but this isn't required by the PCM63. A clock at 256*fs is typically called 'MCLK' for 'Master Clock' - but older style multibit DACs don't need this clock because they have no digital processing internally that requires such a clock.
PCM63 just needs bit clock, data and a frame sync pulse which indicates the data start.
PCM63 just needs bit clock, data and a frame sync pulse which indicates the data start.
Thx abraxalito, when I look at the CS8412 data sheet, it says it can output MCK at 256Fs, SCK at 64Fs, and FS.
But how do you know what the PCM63 needs? Where does it say "I need 256Fs or 384Fs or 64Fs"?
But how do you know what the PCM63 needs? Where does it say "I need 256Fs or 384Fs or 64Fs"?
Have you pulled up the datasheet for the PCM63? Fig 2 on page 7 shows the timing diagram - the top three traces are the inputs: CLOCK, DATA and LE. Seeing as the CS8412 produces CLK at 64fs, you just need to check that this frequency is acceptable to the PCM63 - page 2 shows the maximum permitted is 25MHz. LE isn't produced by the CS8412 - that's the purpose of the logic in the schematic you linked to.
Technically both are possible though if you sent 256fs to it you'd not like the sound of the noise coming out - the digital data is synchronized to the 64fs clock, not the 256fs one. Consult the CS8412 datasheet.
There is a ton of useful stuff on this at:
http://www.diyaudio.com/forums/digital-source/5798-non-oversampling-dac-complementing-cd-pro.html
DAC with two PCM1704
Creating a DIY non oversampling DAC with PCM1704
http://www.diyaudio.com/forums/digital-source/39993-non-oversampling-pcm1704.html
Theoretical Background
High End Audio - Digital decoder for NOS DAC
design | Halide Design
A universal shifting circuit for interfacing decoder X with converter Y.
http://www.diyaudio.com/forums/digital-source/5798-non-oversampling-dac-complementing-cd-pro.html
DAC with two PCM1704
Creating a DIY non oversampling DAC with PCM1704
http://www.diyaudio.com/forums/digital-source/39993-non-oversampling-pcm1704.html
Theoretical Background
High End Audio - Digital decoder for NOS DAC
design | Halide Design
A universal shifting circuit for interfacing decoder X with converter Y.
- Status
- Not open for further replies.
- Home
- Source & Line
- Digital Line Level
- Help a newbie understand digital glue