Help a newbie understand digital glue

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So question 1:
The SPDIF is received by the CS8412, which then generates a clock and data output.
How do you determine what the clock should be for a given DAC?
How do you know if it should be 256*Fs or 384*Fs, where Fs is 44.1kHz?
 
The CS8412 produces a clock at 256*fs, but this isn't required by the PCM63. A clock at 256*fs is typically called 'MCLK' for 'Master Clock' - but older style multibit DACs don't need this clock because they have no digital processing internally that requires such a clock.

PCM63 just needs bit clock, data and a frame sync pulse which indicates the data start.
 
Have you pulled up the datasheet for the PCM63? Fig 2 on page 7 shows the timing diagram - the top three traces are the inputs: CLOCK, DATA and LE. Seeing as the CS8412 produces CLK at 64fs, you just need to check that this frequency is acceptable to the PCM63 - page 2 shows the maximum permitted is 25MHz. LE isn't produced by the CS8412 - that's the purpose of the logic in the schematic you linked to.
 
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