Hi everyone, I'm trying to make a discrete 3-stages amp headphone amp, I've studied some EE courses but basically I'm a dumb student.
I made a simple differential input stage with 2SK170 in Multisim, with resistor on the source side to limit the gain, but I have no idea how to design a second stage to amplify the output signal from the drain of Q1 (the white line), basically I try to make a BJT common-emitter amplifier which is able to amplify the voltage with limited gain by setting the emitter side resistor, but when I change the resistance of R8 and R7, the amplitude of signal from the collector of Q3 only becomes even smaller, where did I get wrong?
I made a simple differential input stage with 2SK170 in Multisim, with resistor on the source side to limit the gain, but I have no idea how to design a second stage to amplify the output signal from the drain of Q1 (the white line), basically I try to make a BJT common-emitter amplifier which is able to amplify the voltage with limited gain by setting the emitter side resistor, but when I change the resistance of R8 and R7, the amplitude of signal from the collector of Q3 only becomes even smaller, where did I get wrong?
Yeah, the voltage gain of Q3 is slightly less than 1. With an NPN you don’t have enough voltage heardroom to go sticking a bigger resistor in the collector, but with a PNP you would (collector resistor to negative rail). THEN add the NPN as an emitter follower, with no resistor in its collector.
Thank u, I use a PNP as Q3, it's working great now, and btw, how can I make sure the output signal is zero DC biased? By simply setting the correct value of resistors on the collector/emitter of Q3, or are there other methods?
The usual method is DC feedback to the gate of Q2. But you have a lot of degeneration in the source, and might not have enough open loop gain to fully correct. It also may go out of differential balance when you do, resulting in distortion. If you use correct resistor values to get the DC point right it goes a long way, but may still have some offset or drift. You can always cap couple the output.
let's go back to basics. you are direct-coupling 2 stages, so the gains and the biasing for the diff amp stage and common emitter stage are entwined/interactive! for educational/learning purposes, it might be good to add a cap to AC couple the stages instead so you can play with biasing and gain of each stage "independently" until you get a good handle on what you're doing. The gain will be impacted by paralleled impedances, so not quite independent, but you can choose resistor ratios to help lessen the impact.😉
When the inputs are balanced each JFET is conducting 5mA. That translates to a 5V drop across the 1K load resistor(s). So you have (about) 10V on the base of Q3, producing a 25V drop across R7. Neglecting base current in Q3 that means you have a 25V drop across R8, so Q3's collector will be equal to (15 - 25) = -10V. This means that Q3 is in saturation because the base-collector junction is forward biased: Vb = 10, Vc = -10.
This is all just back-of-the-napkin. The voltages won't be correct because once Q3 goes into saturation the effective resistance at Q3's base will be much lower than (beta *Re).
To confirm my hypothesis, I did a quick simulation:
Here's the schematic:
In this simulation, Node 2 is Q1's Collector, Node 3 is its base and Node 10 is its emitter. Vc = 3.102, Vb = 3.831, and Ve = 3.0679. From this we can see that Vb > Vc so yes indeed, Q1 is in saturation.
Your amplifier will never work with the values given. You will need to change resistance values and/or current source and/or supply voltages in order for it to work the way you wish.
This is why some basic evaluation, A.K.A. "back of the napkin" sanity checking is helpful. At least at first, until you learn a few things about circuit design.
Good luck with your quest, and keep on trying!
This is all just back-of-the-napkin. The voltages won't be correct because once Q3 goes into saturation the effective resistance at Q3's base will be much lower than (beta *Re).
To confirm my hypothesis, I did a quick simulation:
Here's the schematic:
In this simulation, Node 2 is Q1's Collector, Node 3 is its base and Node 10 is its emitter. Vc = 3.102, Vb = 3.831, and Ve = 3.0679. From this we can see that Vb > Vc so yes indeed, Q1 is in saturation.
Your amplifier will never work with the values given. You will need to change resistance values and/or current source and/or supply voltages in order for it to work the way you wish.
This is why some basic evaluation, A.K.A. "back of the napkin" sanity checking is helpful. At least at first, until you learn a few things about circuit design.
Good luck with your quest, and keep on trying!