Hi,
anybody knows what is done in this player, got 4 x PCM61 and a bunch of 74HC164 after os filter.
anybody knows what is done in this player, got 4 x PCM61 and a bunch of 74HC164 after os filter.
nope,
That's the entry model with RLS: real-time linear smoothing.
http://www.diyaudio.com/forums/showthread.php?postid=495970#post495970
Sorry for the typo, that's probably why you did not find it with search (you searched, didn't you 😉
The rest of the info is in that tread. Never seen one, only have the brochure..
edit: and forget about the claims on my own dac, found out later it did not work as i thought it did
That's the entry model with RLS: real-time linear smoothing.
http://www.diyaudio.com/forums/showthread.php?postid=495970#post495970
Sorry for the typo, that's probably why you did not find it with search (you searched, didn't you 😉
The rest of the info is in that tread. Never seen one, only have the brochure..
edit: and forget about the claims on my own dac, found out later it did not work as i thought it did
guido said:
As I got the player 😀 I can follow the traces and draw a schematic.
I was thinking that maybe the logic chips will translate the data into positive and negative halfwaves, but this hardware double oversampling is interesting too.
If you want it, I have the service manual ( of course 😉 ) of HD7725 with the same output stage/DACs.
Hi Jean Paul,
Could you Pls. also Email me a copy of the HK "oversampling" DAC section.
Cheers,
John
Could you Pls. also Email me a copy of the HK "oversampling" DAC section.
Cheers,
John
guido said:
edit: and forget about the claims on my own dac, found out later it did not work as i thought it did
have you corrected it?
Hi Bernhard,
"Even if it is a rubidium atomic clock, that does not necessarily mean it is low jitter"
As a quick side note, the lowest phase noise atomic clock I'm aware of is the Stanford Research Systems Rubidium Frequency standard PRS10.
I use one phase locked to my 2 FTS4050 Cesium Frequency standards to reduce their “short-term” phase noise – on my module its phase noise is better then -140dB @ 10MHz 10Hz offset!
John
"Even if it is a rubidium atomic clock, that does not necessarily mean it is low jitter"
As a quick side note, the lowest phase noise atomic clock I'm aware of is the Stanford Research Systems Rubidium Frequency standard PRS10.
I use one phase locked to my 2 FTS4050 Cesium Frequency standards to reduce their “short-term” phase noise – on my module its phase noise is better then -140dB @ 10MHz 10Hz offset!
John
Gentlemen, you both have mail.
As always I would appreciate it to receive another service manual in return to add to my prize-winning collection 😉
As always I would appreciate it to receive another service manual in return to add to my prize-winning collection 😉
rfbrw said:
In the end i got what i aimed to build, a non os dac. Think you dont see that as corrected 😉
Jean-Paul, i would be interested in the manual too. Maybe i can give it a try. Tried to mail you, no reply ??
guido said:
In that case it doesn't need correcting. Now if only you would repent and see the error of your ways and come over to the dark side
. The unlimited joys of oversampling awaits you. We even allow the TDarrrrgh if it is preceded by a digital filter.Excellent idea. They are doing what you do with the added goodness of a SM5840 digital filter.
rfbrw said:
In that case it doesn't need correcting. Now if only you would repent and see the error of your ways and come over to the dark side
Excellent idea. They are doing what you do with the added goodness of a SM5840 digital filter.
Even if the dig filter is an SAA722ughhhh? Anyway, i'm working isev6 to put all logic (and more, e.g. dem reclocking) into an 95108 from xilinx. That's including the cmos shift register i'm using now (which is too slow for oversampling, non-os is to the limit).
So if i get that finished, i can give it a try with os 🙂
Problem is i only have (plenty...) of those SAA7220's around...
Philips country, you know.I'm not doing what HK is doing with this player. I have a non-os dac with balanced (not completely in your view, another discussion) TDA's. And as a gimmic i can switch to a fir filter with a jumper.
As for the HK approache, i think i can rebuild the dig part with the logic i have on my dac. But those players got a 'not so good' review in those days, so i dont know if it is worth the effort. The analog part is with lots of transistors.
Bernard,
How does the thing sound ????
guido said:
There was something about the dem stuff working better with logic with a narrower voltage swing. If you use the 3.3v 9500XL series, you get the narrower swing.
So if i get that finished, i can give it a try with os 🙂
Problem is i only have (plenty...) of those SAA7220's around...
How about the TDA1307?
Not the +1 thing again.
guido said:
Did not seriously listen, but measured...
High order harmonics up to k13, adjustment useless, no wonder... PCM61.
rfbrw said:
Your mixing up two things: the dem reclocking (swap cap for active circuit to bypass the internal oscillator for the dem stage) vs the voltages on the I2S inputs. Since i'm including a ff after the xilinx to reclock, i might do something there with a lower voltage ff instead of decreasing it after the ff.
Currently i'm fighting isev6 and modelsim. Got the latest version, but had to upgrade to win2000 to get it running. I'll get there.
At least the pcb is easy with such a cpld, nothing left to route😀
never seen one, but who knows...
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