As some of you may know I've been working on a design which uses a FIFO to solve the jitter problems in external DACs. It currently consists of an AD9850 chip for clock generation (as used by Mark Levinson), the FIFO, an AVR micro-controller and about 13 logic ICs.
The design is progressing slowly but so far it works very well. However I would like to swap the 13 logic ICs for a single CPLD to save a large amount of board space as well as provide an easy way to change the circuitry should that be required.
Could anyone here give me any pointers on using these devices?
Digi-key stock a good selection of the Xilinx CPLDs and Xilinx also have software that can be downloaded free of charge.
I haven't been able to find any good info on a programmer for them although I'm sure Xilinx sell them but I doubt they are cheap. Does anyone know of a schematic for a programmer? Can the device be connected straight to the parallel port like Atmel AVRs?
Also I don't know any VHDL or HDL so I'd like to design the device with a schematic style entry system. Is this do-able?
Any help would be much appreciated.
The design is progressing slowly but so far it works very well. However I would like to swap the 13 logic ICs for a single CPLD to save a large amount of board space as well as provide an easy way to change the circuitry should that be required.
Could anyone here give me any pointers on using these devices?
Digi-key stock a good selection of the Xilinx CPLDs and Xilinx also have software that can be downloaded free of charge.
I haven't been able to find any good info on a programmer for them although I'm sure Xilinx sell them but I doubt they are cheap. Does anyone know of a schematic for a programmer? Can the device be connected straight to the parallel port like Atmel AVRs?
Also I don't know any VHDL or HDL so I'd like to design the device with a schematic style entry system. Is this do-able?
Any help would be much appreciated.
well, i am by no means an expert, but i have never seen a schematic-style entry system (for pld's) before. It just might be that you have to learn VHLD. If you have any programming experience, then it won't be to much of a difficulty. But if you don't, then it might be a bit of trouble(but not impossible!)
As for price, CPLDs can do some pretty amazing things. (the "C" is for complex) You might be able to get away with a small PLD (SPLD), which are quite a bit cheaper but i can't say for sure without seeing the schematic. You might be surprised at what the "simple" devices can do(and how much discrete logic they can replace).
Some CPLD even be programmed in circuit. There are certain models which can be programmed via the port of your computer, with no special programmer needed.
All told, learning to use VHDL and using PLDs can be very rewarding. I have contructed a rotary encoder to PGA2310 interface with a SPLD (22V10) which saves a crapload of discrete logic.
Good Luck!
As for price, CPLDs can do some pretty amazing things. (the "C" is for complex) You might be able to get away with a small PLD (SPLD), which are quite a bit cheaper but i can't say for sure without seeing the schematic. You might be surprised at what the "simple" devices can do(and how much discrete logic they can replace).
Some CPLD even be programmed in circuit. There are certain models which can be programmed via the port of your computer, with no special programmer needed.
All told, learning to use VHDL and using PLDs can be very rewarding. I have contructed a rotary encoder to PGA2310 interface with a SPLD (22V10) which saves a crapload of discrete logic.
Good Luck!
PLD Programming
Dave, while I haven't done anything with Xilinx, I have been installing upgrades to pro audio digital gear using Lattice PLDs. These can be programmed in circuit in a daisy chain. The boards in question have 7 Lattice PLDs and they can all be programmed in a single operation, through a simple interface driven from the parallel port on a PC. The programming software is free from www.latticesemi.com, and they seem to have a 6 month demo of the design software.
The circuits I've been working with are involved with clock sync & distribution in AES/EBU interfaces, so should be suitable for your job.
Could be worth a look, & Lattice products are available in NZ from Farnell.
Colin
Dave, while I haven't done anything with Xilinx, I have been installing upgrades to pro audio digital gear using Lattice PLDs. These can be programmed in circuit in a daisy chain. The boards in question have 7 Lattice PLDs and they can all be programmed in a single operation, through a simple interface driven from the parallel port on a PC. The programming software is free from www.latticesemi.com, and they seem to have a 6 month demo of the design software.
The circuits I've been working with are involved with clock sync & distribution in AES/EBU interfaces, so should be suitable for your job.
Could be worth a look, & Lattice products are available in NZ from Farnell.
Colin
Dave,
Never worked with CPLDs, but as SoundOff points out, you can use PLDs (Gals) chained or paralleled. As I do not know what kind of logic functions you want to perform, I can only stop here.
Concerning PLDs, I can tell a little more
. I found a DIY programmer that I built. It works more than fine and is much cheaper than any commercial one. I only tested it with Lattice GALs, though it is not "Lattice approved", with absolutely no problem.
Concerning the design side, I used Protel, which I have access to at work. I didn't need VHDL or CUPL (though it can help), I just drawn the schematic of the logic functions I wanted, and compiled it to get a Jedec file. That's all. You can also do simulation of the design. I was a little bit frightened since it was all new to me, but the learning curve is exponential, and the provided examples help a lot.
P.S. : I redesigned the PCB of the programmer to be able to handle PLCC packages. If you're interested, drop me an e-mail.
Hope this helps
Never worked with CPLDs, but as SoundOff points out, you can use PLDs (Gals) chained or paralleled. As I do not know what kind of logic functions you want to perform, I can only stop here.
Concerning PLDs, I can tell a little more
. I found a DIY programmer that I built. It works more than fine and is much cheaper than any commercial one. I only tested it with Lattice GALs, though it is not "Lattice approved", with absolutely no problem.Concerning the design side, I used Protel, which I have access to at work. I didn't need VHDL or CUPL (though it can help), I just drawn the schematic of the logic functions I wanted, and compiled it to get a Jedec file. That's all. You can also do simulation of the design. I was a little bit frightened since it was all new to me, but the learning curve is exponential, and the provided examples help a lot.
P.S. : I redesigned the PCB of the programmer to be able to handle PLCC packages. If you're interested, drop me an e-mail.
Hope this helps
The best way to program Xilinx, Lattice and Altera CPLDs is through the JTAG port (aka boundry scan). This envolves taking the +V, GND, TDI, TDO, TCLK and TMS signals from the CPLD to a header.
Xilinx will sell you a programmer cable for around $100 (see
http://www.xilinx.com/xlnx/xil_prod...Pick=System+Solutions&sGlobalNavPick=PRODUCTS
If that monster URL doesn't work then go to products, system resources, configuration solutions then cable support). The programmer software (called Impact webpack) is also free.
Xilinx used to include the programmer schematic on their website but I can't find it at the moment - let me know if you'd like a copy and I'll email you a GIF. It's a very simple parallel port design: just a couple of TTL buffers and resistors.
As for devices, a XC9536 (5v), XL (3.3v) or XV (2.5v) will easily mop all 13 logic chips. For lower power, use Coolrunner or the newer Coolrunner 2 families.
Hope this helps.
Dave
Xilinx will sell you a programmer cable for around $100 (see
http://www.xilinx.com/xlnx/xil_prod...Pick=System+Solutions&sGlobalNavPick=PRODUCTS
If that monster URL doesn't work then go to products, system resources, configuration solutions then cable support). The programmer software (called Impact webpack) is also free.
Xilinx used to include the programmer schematic on their website but I can't find it at the moment - let me know if you'd like a copy and I'll email you a GIF. It's a very simple parallel port design: just a couple of TTL buffers and resistors.
As for devices, a XC9536 (5v), XL (3.3v) or XV (2.5v) will easily mop all 13 logic chips. For lower power, use Coolrunner or the newer Coolrunner 2 families.
Hope this helps.
Dave
I forgot to mention that Xilinx also has a reduced version of the ModelSim VHDL simulation tool available for free:
http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=modelsim_xe
The free version runs slower than the full edition and has a code length limit, but it's something like 100000 lines!!
http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=modelsim_xe
The free version runs slower than the full edition and has a code length limit, but it's something like 100000 lines!!
I don't know if it's available on CPLDs (it is on FPGAs), but you might want to consider using Verilog instead of VHDL. Many people find the C-like syntax of Verilog easier to deal with than the Ada-like syntax of VHDL (it was for me since I am a C++ programmer). Verilog is newer, but since it's growing much faster has managed to already capture roughly half the HDL market. I can't provide much more input than that, having never used VHDL, I can only echo comments made by people who have used both.
-Won
-Won
For 13 logic IC's a good place to start would be to use CPLD's as opposed to FPGA's. The devices from Altera, Cypress,Lattice and Xilinx tend to be JTAG-configurable, which means you do not need a programmer, just a cable whose schematic you can get from manufacturer websites.
Not sure about Altera but the free software from Lattice and Xilinx definitely have a schematic entry option.
ray
Not sure about Altera but the free software from Lattice and Xilinx definitely have a schematic entry option.
ray
Just some guesses regarding Dave's design. If I didn't misunderstand, timing is critical in this app. ROM/RAM should be far too slow, and uC also. Futhermore, you should make the uC work synchronously, and provided the chip is fast enough, it should be quite heavy from the programming side. But sure Dave can tell us a little more about his choice
A good book...
Check out HDL Chip Design by Douglas J. Smith. It covers both VHDL and Verilog side by side as you go through. It has plently of examples.
Pretty much any CPLD tool will have schematic capture capabilities. I know Lattice, Altera, and Xilinx do. Question is whether you can get the tool for free (demo) or not.
If your design is nothing more than combinatory gates, I recommend VHDL. There is some syntax to follow, but it's pretty general. If you can find some piece of VHDL code to learn from, just reuse the library/entity/achitecture definitions. Heck, most tools have templates setup so you can't mess up! Everything else is just defining 'signals' and AND'ing or OR'ing them together (don't forget the blasted semi-colons! )
Now, if your design requires sequencial state machines and you already have a working schematic using flip-flops and such, then the schematic capture route will bring your PLD to life quicker if you are not familiar with HDLs. However, VHDL has some real nifty ways of handling sequencial systems and it wouldn't hurt to know how to take advantage (for future implementations).
Check out that book if you go with the VHDL (or Verilog) method.
Dave
Check out HDL Chip Design by Douglas J. Smith. It covers both VHDL and Verilog side by side as you go through. It has plently of examples.
Pretty much any CPLD tool will have schematic capture capabilities. I know Lattice, Altera, and Xilinx do. Question is whether you can get the tool for free (demo) or not.
If your design is nothing more than combinatory gates, I recommend VHDL. There is some syntax to follow, but it's pretty general. If you can find some piece of VHDL code to learn from, just reuse the library/entity/achitecture definitions. Heck, most tools have templates setup so you can't mess up! Everything else is just defining 'signals' and AND'ing or OR'ing them together (don't forget the blasted semi-colons!
) Now, if your design requires sequencial state machines and you already have a working schematic using flip-flops and such, then the schematic capture route will bring your PLD to life quicker if you are not familiar with HDLs. However, VHDL has some real nifty ways of handling sequencial systems and it wouldn't hurt to know how to take advantage (for future implementations).
Check out that book if you go with the VHDL (or Verilog) method.
Dave
Thanks for the replies, most helpful.
So far I think the Xilinx devices look promising although Lattice do look good as well. It seems all the required Xilinx software is avaliable for free (about 90MB which I'm going to have to download over a 56K modem) and I found this schematic of thier parallel cable III (attached). The new IV version is out now but I couldn't find the schematic for that.
daatkins, what version do you have?
MRehorst, I'm not an expert on the subject but I think CPLDs are suited to high speed custom logic applications where a uC would not be able to keep up. ROM is too slow but is a nice simple way to make up logic replacing a whole heap of gates, you can just copy a truth table into the chip, although I've never used this method myself.
So far I think the Xilinx devices look promising although Lattice do look good as well. It seems all the required Xilinx software is avaliable for free (about 90MB which I'm going to have to download over a 56K modem) and I found this schematic of thier parallel cable III (attached). The new IV version is out now but I couldn't find the schematic for that.
daatkins, what version do you have?
MRehorst, I'm not an expert on the subject but I think CPLDs are suited to high speed custom logic applications where a uC would not be able to keep up. ROM is too slow but is a nice simple way to make up logic replacing a whole heap of gates, you can just copy a truth table into the chip, although I've never used this method myself.
Dave, check www.epanorama.net
There is a lot of goof stuff on FPGA's.
I know that Conrad , an electronics retailer here in holland /germany, sells fpga boards of Altera with SW.
Altera's MAXplusII package has all you need !
From design to the programming part.
A couple of years ago it was even possible to let it make a circuit by drawing the signals in sort of a wave editor.
grtz
Simon
There is a lot of goof stuff on FPGA's.
I know that Conrad , an electronics retailer here in holland /germany, sells fpga boards of Altera with SW.
Altera's MAXplusII package has all you need !
From design to the programming part.
A couple of years ago it was even possible to let it make a circuit by drawing the signals in sort of a wave editor.
grtz
Simon
I finally fired up a Xilinx XC9572 CPLD so I thought I'd update the thread.
Firstly I learn't a bit a VHDL which proved to be easier than I expected.
I used the free software from the Xilinx site which is pretty straight forward to use. Version 5.1i didn't run on my machine so I ended up with 4.2i and service pack 3. This worked fine.
The CPLDs are of course in system programable, all you need to do is build the cable to connect it to your parallel port. The schematic of this posted above.
Firstly I learn't a bit a VHDL which proved to be easier than I expected.
I used the free software from the Xilinx site which is pretty straight forward to use. Version 5.1i didn't run on my machine so I ended up with 4.2i and service pack 3. This worked fine.
The CPLDs are of course in system programable, all you need to do is build the cable to connect it to your parallel port. The schematic of this posted above.
Hello Dave,
I had a look at your website and it's a nice little project you've got going there!
I know it's a bit late to suggest this, but an alterntive approch to the FIFO would be to use an FPGA and implement some internal dual-port RAM. The Xilinx ISE software (4.2i, for example) includes a tool called Coregen: just type in a few parameters like port sizes, address range, clock/reset details and Coregen will write the DP RAM code for you. This can only be done with FPGAs because they contain large amounts of block RAM which can be configured as the user wants. Even the smaller devices have several hundred Kb of block RAM memory with larger devices going upto 10Mb.
The main problem with using FPGAs is the extreamly high density of the pins in relitively small packages making most of them impossible to produce DIY circuit boards for (I'm currently designing a circuit at work using a Virtex 2 Pro with 1517 pins).
One trick I've used when applying CPLDs to DIY designs is to mount the BGA package upside-down and link wire from the solder balls onto the PCB. This works fine with slow circuits but inductance and poor power supply decoupling will be a problem at more than about 10MHz.
Nice one,
David
I had a look at your website and it's a nice little project you've got going there!
I know it's a bit late to suggest this, but an alterntive approch to the FIFO would be to use an FPGA and implement some internal dual-port RAM. The Xilinx ISE software (4.2i, for example) includes a tool called Coregen: just type in a few parameters like port sizes, address range, clock/reset details and Coregen will write the DP RAM code for you. This can only be done with FPGAs because they contain large amounts of block RAM which can be configured as the user wants. Even the smaller devices have several hundred Kb of block RAM memory with larger devices going upto 10Mb.
The main problem with using FPGAs is the extreamly high density of the pins in relitively small packages making most of them impossible to produce DIY circuit boards for (I'm currently designing a circuit at work using a Virtex 2 Pro with 1517 pins).
One trick I've used when applying CPLDs to DIY designs is to mount the BGA package upside-down and link wire from the solder balls onto the PCB. This works fine with slow circuits but inductance and poor power supply decoupling will be a problem at more than about 10MHz.
Nice one,
David
MWP,
Yes, I think nearly all have schematic entry options, I've used the Altera one at uni.
Daatkins,
I hadn't thought of that approach, its a nice idea but I think I'll stick with a dedicated FIFO chip for now. I'm using a FIFO from Texas Instruments.
Also the free ISE software doesn't include the coregen feature although I think you can still configure the RAM through VHDL code.
Yes, I think nearly all have schematic entry options, I've used the Altera one at uni.
Daatkins,
I hadn't thought of that approach, its a nice idea but I think I'll stick with a dedicated FIFO chip for now. I'm using a FIFO from Texas Instruments.
Also the free ISE software doesn't include the coregen feature although I think you can still configure the RAM through VHDL code.
another FIFO design on it's way..
Dave,
I am working on something similiar. I am working on a DAC with
two times TDA1541 in non-os. It has two things which are
different than most other designs with that setup:
- split I2S into left and right. So one DAC is left and one is right
channel. Output of one DAC's left and right channel can be equal or
inverted. I have this working, posted a while ago.
- use of an async FIFO to get rid of jitter getting in. I am using
the CY7C429, a second source for the AMD AM720x series. I am now working
on the board, see the digital grounding threat here (last update 14-10).
I am developing this to connect it to an old philips style CD player, feeding
the clock back to the player. In this way the clock of the DAC and player have
exactly the same frequency, so i don't get the FIFO getting full or empty.
Just stop the reading clock when empty (reset condition) and start at halffull.
One '74 FF reads the empty and halffull flag and creates a 'on' signal for the
reading clock being enabled.
I am using a SPLD (GAL 20V8), but mainly for the I2S splitting. I have a programmer
for years now and they still suit my needs. The chipcount: the FIFO, the GAL and
about 5 logic IC's. Guess the GAL and logic can be replaced easily with a CPLD,
but i've settled for the GAL.
As a clock source, i have Guido Tent's oscillator on board and i will look into other
oscillators later. It was choosen mainly because of the small size.
If i have it working, i'll start a post. But i guess it is not going to be as universal
as what you are working on. I find your whole solution quite interesting.
Greetings,
Guido B.
Dave,
I am working on something similiar. I am working on a DAC with
two times TDA1541 in non-os. It has two things which are
different than most other designs with that setup:
- split I2S into left and right. So one DAC is left and one is right
channel. Output of one DAC's left and right channel can be equal or
inverted. I have this working, posted a while ago.
- use of an async FIFO to get rid of jitter getting in. I am using
the CY7C429, a second source for the AMD AM720x series. I am now working
on the board, see the digital grounding threat here (last update 14-10).
I am developing this to connect it to an old philips style CD player, feeding
the clock back to the player. In this way the clock of the DAC and player have
exactly the same frequency, so i don't get the FIFO getting full or empty.
Just stop the reading clock when empty (reset condition) and start at halffull.
One '74 FF reads the empty and halffull flag and creates a 'on' signal for the
reading clock being enabled.
I am using a SPLD (GAL 20V8), but mainly for the I2S splitting. I have a programmer
for years now and they still suit my needs. The chipcount: the FIFO, the GAL and
about 5 logic IC's. Guess the GAL and logic can be replaced easily with a CPLD,
but i've settled for the GAL.
As a clock source, i have Guido Tent's oscillator on board and i will look into other
oscillators later. It was choosen mainly because of the small size.
If i have it working, i'll start a post. But i guess it is not going to be as universal
as what you are working on. I find your whole solution quite interesting.
Greetings,
Guido B.
Sounds neat. Certianly the way to go if you're feeding the clock back to the transport.
Mine is standalone so that it will work with any source component. This makes things much more complicated which is why I've had to span the FIFO control gear across an AVR uC and an XC9572 CPLD. The AVR also takes care of other things like input selection, reset routines and possibly an LCD and RC5 remote decoder running on it in the future as well. There's also another XC9572 to mop up general glue logic too.
I hope to have PCBs done by the end of the year.
Mine is standalone so that it will work with any source component. This makes things much more complicated which is why I've had to span the FIFO control gear across an AVR uC and an XC9572 CPLD. The AVR also takes care of other things like input selection, reset routines and possibly an LCD and RC5 remote decoder running on it in the future as well. There's also another XC9572 to mop up general glue logic too.
I hope to have PCBs done by the end of the year.
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