As some of you may know I've been working on a design which uses a FIFO to solve the jitter problems in external DACs. It currently consists of an AD9850 chip for clock generation (as used by Mark Levinson), the FIFO, an AVR micro-controller and about 13 logic ICs.
The design is progressing slowly but so far it works very well. However I would like to swap the 13 logic ICs for a single CPLD to save a large amount of board space as well as provide an easy way to change the circuitry should that be required.
Could anyone here give me any pointers on using these devices?
Digi-key stock a good selection of the Xilinx CPLDs and Xilinx also have software that can be downloaded free of charge.
I haven't been able to find any good info on a programmer for them although I'm sure Xilinx sell them but I doubt they are cheap. Does anyone know of a schematic for a programmer? Can the device be connected straight to the parallel port like Atmel AVRs?
Also I don't know any VHDL or HDL so I'd like to design the device with a schematic style entry system. Is this do-able?
Any help would be much appreciated.
The design is progressing slowly but so far it works very well. However I would like to swap the 13 logic ICs for a single CPLD to save a large amount of board space as well as provide an easy way to change the circuitry should that be required.
Could anyone here give me any pointers on using these devices?
Digi-key stock a good selection of the Xilinx CPLDs and Xilinx also have software that can be downloaded free of charge.
I haven't been able to find any good info on a programmer for them although I'm sure Xilinx sell them but I doubt they are cheap. Does anyone know of a schematic for a programmer? Can the device be connected straight to the parallel port like Atmel AVRs?
Also I don't know any VHDL or HDL so I'd like to design the device with a schematic style entry system. Is this do-able?
Any help would be much appreciated.