Thank you very much Sorento!That table shows i'd be still below the lowest air gap there at 0.008mm.
with the minimum gap I still don't have enough turns to get the inductance right for Fmin=20hz...so i need to laminate for no gap to increase the inductance 4 times.
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dreamth,
If you get the air gap small enough, you may get enough inductance to work down to 20Hz, as long as there is no quiescent DC current in the primary.
But when you apply DC current, and then if the Amp x Turns causes the core to saturate, than that will reduce the inductance (a loosing battle).
Get enough more laminations, get enough turns so that there will be enough inductance, and that the core will not saturate.
With a SE output stage, and core saturation at 20Hz, you can see the characteristic divot on the sine wave (an 'eating away' of the sine wave as it falls after the crest).
That is 2nd Harmonic distortion (40Hz 2nd harmonic of 20Hz).
If you get the air gap small enough, you may get enough inductance to work down to 20Hz, as long as there is no quiescent DC current in the primary.
But when you apply DC current, and then if the Amp x Turns causes the core to saturate, than that will reduce the inductance (a loosing battle).
Get enough more laminations, get enough turns so that there will be enough inductance, and that the core will not saturate.
With a SE output stage, and core saturation at 20Hz, you can see the characteristic divot on the sine wave (an 'eating away' of the sine wave as it falls after the crest).
That is 2nd Harmonic distortion (40Hz 2nd harmonic of 20Hz).
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The design is balanced drive so i'm thinking more of the possible imbalanced currents...but i might probably look at removing all the standing currents from the primary.
There's no simple answer, as it depends of the manufactured quality of the laminations and coresm, such as burred edges, lamination insulation thickness, and cutting + polishing for C cores. I've worked with technical air gaps anywhere from 25um from stacked interleaved 80% Nickel EIs to 0.5mm gap amorphous C cores which, when pointed towards a light source, let light shine through the gaps. 😀
You can calculate it though, by measuring inductance (at specific flux density) and magnetic path length, then calculate the permeability and compare with the absolute permeability at this flux density (from manufacturer's datasheet)".
The measured permeability will usually be lower and you can then calculate the "technical airgap" causing it.
Do you need formulas?
I found a few formulas, it's just that i don't really have data about my lamination(taken from scrapped transformers) and i'd have to measure everything which is not really simple, but these last two days i made a lot of approximate calculation to help me solve some problems and i'll certainly go balanced mode with as small as possible idle current.I have some limiting factors as i already placed 90% of the windings ...still calculating.
The gap is just stopping eddy currents.
I would have thought any gap would do that ?
So long as voltage cant jump the gap.
I would have thought any gap would do that ?
So long as voltage cant jump the gap.
No - the gap is there to set a specific amount of inductance for a given core area and number of turns. It also allows the primary winding to support a DC bias current without saturating. Design finesse involves playing off inductance vs. DC bias current capability. You want high inductance to support low frequency operation ( pushes toward smaller gap), but you need decent DC bias capability for significant output power. (pushes toward larger gap). You also get to play with core area and number of turns to optimize the design, as well as interleaving to reduce leakage inductance (at the same time, increasing interwinding capacitance). It's a merry dance for optimization....
Use of laminations is about reducing eddy currents, and the laminations have an oxide finish to insulate between lams to reduce eddy current. The thinner the lams, the less eddy current. However, the thinner lams will have a lower stacking factor due to the thickness of the insulating layer vs. lam thickness.
Use of laminations is about reducing eddy currents, and the laminations have an oxide finish to insulate between lams to reduce eddy current. The thinner the lams, the less eddy current. However, the thinner lams will have a lower stacking factor due to the thickness of the insulating layer vs. lam thickness.
dreamth, the simplest way to find the needed gap is by determining the maximum flux density for primary Rms first.
Here's an example. Let's say you decided on your maximum flux density to be 1.2T (AC + DC signal).
Let's say your AC signal results into 1.0T. If so, you're left with a 0.2T DC headroom.
Now, by knowing this, you can determine the maximum inductance for your maximum chosen value of Idc using the formula Bdc = L x I / Turns x Afe
Example: A transformer with a core of 10sq.cm, 3000 primary turns, and a 5mA maximum Idc across the primary:
0.2 = L x 0.005 / 3000 x 0.001
L = 120H
Remember it is linear, so for 10mA Idc L= 60H
Keep in mind that if inductance is already within a satisfactory range, the technical gap or initial material permeability has already taken care of your problem and you do not need to worry.
Remember to measure inductance at an acceptable excitation, 0.2T at least, especially for silicon steel, to stay away from the initial BH knee.
Here's an example. Let's say you decided on your maximum flux density to be 1.2T (AC + DC signal).
Let's say your AC signal results into 1.0T. If so, you're left with a 0.2T DC headroom.
Now, by knowing this, you can determine the maximum inductance for your maximum chosen value of Idc using the formula Bdc = L x I / Turns x Afe
Example: A transformer with a core of 10sq.cm, 3000 primary turns, and a 5mA maximum Idc across the primary:
0.2 = L x 0.005 / 3000 x 0.001
L = 120H
Remember it is linear, so for 10mA Idc L= 60H
Keep in mind that if inductance is already within a satisfactory range, the technical gap or initial material permeability has already taken care of your problem and you do not need to worry.
Remember to measure inductance at an acceptable excitation, 0.2T at least, especially for silicon steel, to stay away from the initial BH knee.
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