Full digital 2kW AMP - how to combine TI PurePath PWM Modulator with custom designed power stage?

Hi guys,

I am looking for a low SNR high power Amp Design that offers a full digital path.
So I want you use a DSP (like SigmaDSP) to deliver I2S signals to a PWM Modulator Chip (e.g. TAS555x from Texas Instruments).

These PWM modulators normally have integrated Noise Shapers and offer PWM signals to drive a power stage.
But they normally dont offer any means of feedback from the final AMP output to eliminate distortions or voltage fluctuations of power supply fluctuations.

Normally you add a Power stage like TAS5634 (2x300W) - the include the output stage, full protection and a feedback from output to PWM signals.


The Idea:
  • Use a PWM Modulator Chip to produce PWM Signals for output stage
  • Feed PWM Signals into discret MOSFET Power stage with fast and low jitter gatedrivers
  • Add protection against crosscunduction, overtemperature and overcurrent
Questions:
  • How can a feedback be implemented to modify PWM signals?
  • Can a outputsignal feedback be avoided by sampling supply voltage and feedback measurement to DSP stage (BW < 1kHz)?

Any other cool ideas or design recommendations?
 
Below Picture is from the TAS5634 datasheet - the power stage following the PWM modulator chip. Can anyone explain what TI is technically doing between Input Pin and Gatedriver stage?
The analog loop Filter with Comparator seems to implement the output feedback control.

1738768419451.png
 
I was thinking a bit - I had a misconception about the input PWM signals.
Now I understand that this is the desired PWM waveform of the halfbridge output.
My error was assuming that C and D were the complementary signals of a half bridge.

There are multiple effects, that will introduce error into the output signal, that need to be corrected.
Part of the effects and their way to correct are clear to me; others I don't have a clue by now:

1. Effect of dead time to prevent half bridge cross conduction (thats clear to me):
=> When applying the PWM signal to a half bridge, the gatedrivers must introduce a small dead time where no switch is conducting.
During this small pause no switch is on, the current will commutate from the closed switch to a free wheeling diode. Which diode depends on the direction of the current. This will distort the output voltage as voltagetime integration deviates from intended signal.
To compensate a measurement of current direction is required and then the dutycycle needs to be corrected by +/- dt/2.


2. PSRR - Pushing effect of power supply (unclear)
=> The PWM dutycycle is ideally multiplied with supplyvoltage. Any distortion of the Supply Voltage is directly found in output signal. Especially when the powersupply is dynamically loaded the output voltage can fluctuate heavily and modulate the output signal.
A compensation requires an extension or shortening of PWM pulses.


3. Linear errors (e.g. load; voltage drop etc.)
=> The output stage has internal resistances (Rds,On, PCB tracks, Inductor resistance) and the speaker is a complex load which can behave like a capacitor or inductor. All these effects will change the actual output voltage from what the modulator intended.


What do you think - how does the "Analog Loop FIlter" and "PWM & Timing Control" accomplish this?
Is it a PWM demodulator comparing analog signals from PWM and output?
Syncronized with PWM input signal?