I can not seem to find a definitive answer for this problem in any searches. I want to discover a means to determine the best magnitude for bias current (and I do not mean the output stage quiescent operating point). So I now consult my pool of experts on DIYAudio... My apologies for being long-winded; I have found that trying to tweak a question to fit answers is less effective than just getting it all out there for everyone to consider.
Consider an everyday LIN 3-stage power amp with voltage feedback: Standard LTP input, followed by VAS, and finally a compatible OPS. The output stages are easy to find information about and I am not seeking a class debate or discussion. Please do not talk about class because you will have avoided my question. The more elusive information concerns the quiescent current through the LTP and VAS. In our LTPs, we all basically provide current source/sink for our DCOP. From there is some sort of essentially fixed relationship yielding a VAS DCOP, with a variety of possibilities. I visualize the ideal front end as an electronic pantograph in this regard.
I have gathered these tidbits but they are not sufficient to form my own conclusion:
(1A) Considering the LTP: If dominant-pole capacitance is used, in principle it must be charged from the LTP source/sink to accomodate the VAS swing and this is a trivial computation [weakly] assuming that the VAS does not otherwise limit; ultimately this defines a pre-emptive limiting slew rate if the overall transfer function wanders out of phase before giving up gain at HF, and we could segue to the OL gain debate but let's not. This is not the mystery: Certainly a DPC value exists for any value of current to set the slew rate limit appropriately, so this does not directly help me. With current and capacitance set, there is some resulting max frequency at peak voltage. OK, fine. I can limit my slew rate with the capacitor after I have settled on the LTP DC operating point (or simply use alternate techniques to avoid the DPC remedy altogether). As a result most examples of design DCOP here seem arbitrary to me.
(1B) Considering the VAS: The current must be able to supply impetus at the highest frequency of interest to the OPS in order to continuously get it where it needs to be to minimize error. A small collection of EE rudiments seems to serve this decision quite well. Be it buffering for gate capacitances, minority carrier issues in darlington outputs, etc., this can be nailed down pretty effectively; whatever it takes such that the VAS will not be overloaded and made non-linear in its relationship with the OPS.
(2) I have come to accept that noise issues arise at "low" currents as Johnson-Nyquist noise becomes a relatively large factor in resistive components at real-world temperatures over a given bandwidth. Increased current should cause decreased relative contribution of these sources. Obviously this depends somewhat on resistor value choices for degeneration and loading since it appears in the equation. Mathematically it seems the noise current for a given resistor decreases as the square root of resistance increases, which would accompany bias current decreasing linearly if we are considering a fixed goal of dynamic error voltage range across the LTP inputs (to a great degree I share W. M. Leach's philosophy on establishing dynamic range with degeneration, since I firmly believe that skipping it and expecting linear results with real transistors is like pushing a panel upstream from the trailing edge), for instance if a 100mV dynamic error range is desired, 100ohms of degen would be needed if the DCOP is 1mA. If I am anywhere near grasping this, I can see that decreasing the DCOP increases the relative noise thus, right?
-By the way I am definitely interested in all OBJECTIVE input regarding resistor technology choice (metal film, carbon, etc.) relative to noise contribution... Using a brute-force technology basis to minimize noise is more elegant IMO than using calculations/optimizations to minimize noise, like exercising and avoiding saturated fat in your diet instead of eventually having liposuction to get a date. For instance, if I know that carbon resistors are the most noisy I simply will not use them in my builds. I am quite skeptical of what I might hear about this however since the equation for J-N noise only includes the resistance value, bandwidth of concern, absolute temperature, and the Boltzmann CONSTANT. I am open to the notion that in an intrinsic 'differential element' view (the space integral of which represents an entire resistor), resistors (like everything else in the real world) may present spatial discretization issues apart from classic parasitics, which would open the door for technology to have an influence on this, arising from various components of isotropy since no resistor is of infinitesimal size.
(3) Heat dissipation is an obvious issue at "high" currents, where any given (Vce * Ic) product approaches ratings.
(4) It intuitively seems that linearity may suffer at "low" currents. I understand that theoretical OL gain may be increased (whether or not it is desirable) at low currents with other parameters fixed, but I also guess that linearity may suffer as devices are operated at miniscule proportions of their design, if only by reducing relative effects of any fixed-value degeneration in use. Clearly this must also consider the Hfe factor(s) to not allow quiescent currents to encounter impotence against interstage loading if drive currents relatively approach quiescent tail currents.
Clearly an optimum is suggested; low enough to survive years of dissipation (particularly if you are like me and think it's better to leave your gear energized to specification as continuously as possible for its service lifetime), while high enough to sound nice. So far I have simply referred to as many similar designs as possible to drive or at least suggest my settings with some success (most of which seem to be between 1mA and 5mA in the LTP(s)), but I'd like to learn more about this matter that is probably more critical than indicated by most discussions which are focused on other general principles.
Are there still factors I have yet failed to mention?
Consider an everyday LIN 3-stage power amp with voltage feedback: Standard LTP input, followed by VAS, and finally a compatible OPS. The output stages are easy to find information about and I am not seeking a class debate or discussion. Please do not talk about class because you will have avoided my question. The more elusive information concerns the quiescent current through the LTP and VAS. In our LTPs, we all basically provide current source/sink for our DCOP. From there is some sort of essentially fixed relationship yielding a VAS DCOP, with a variety of possibilities. I visualize the ideal front end as an electronic pantograph in this regard.
I have gathered these tidbits but they are not sufficient to form my own conclusion:
(1A) Considering the LTP: If dominant-pole capacitance is used, in principle it must be charged from the LTP source/sink to accomodate the VAS swing and this is a trivial computation [weakly] assuming that the VAS does not otherwise limit; ultimately this defines a pre-emptive limiting slew rate if the overall transfer function wanders out of phase before giving up gain at HF, and we could segue to the OL gain debate but let's not. This is not the mystery: Certainly a DPC value exists for any value of current to set the slew rate limit appropriately, so this does not directly help me. With current and capacitance set, there is some resulting max frequency at peak voltage. OK, fine. I can limit my slew rate with the capacitor after I have settled on the LTP DC operating point (or simply use alternate techniques to avoid the DPC remedy altogether). As a result most examples of design DCOP here seem arbitrary to me.
(1B) Considering the VAS: The current must be able to supply impetus at the highest frequency of interest to the OPS in order to continuously get it where it needs to be to minimize error. A small collection of EE rudiments seems to serve this decision quite well. Be it buffering for gate capacitances, minority carrier issues in darlington outputs, etc., this can be nailed down pretty effectively; whatever it takes such that the VAS will not be overloaded and made non-linear in its relationship with the OPS.
(2) I have come to accept that noise issues arise at "low" currents as Johnson-Nyquist noise becomes a relatively large factor in resistive components at real-world temperatures over a given bandwidth. Increased current should cause decreased relative contribution of these sources. Obviously this depends somewhat on resistor value choices for degeneration and loading since it appears in the equation. Mathematically it seems the noise current for a given resistor decreases as the square root of resistance increases, which would accompany bias current decreasing linearly if we are considering a fixed goal of dynamic error voltage range across the LTP inputs (to a great degree I share W. M. Leach's philosophy on establishing dynamic range with degeneration, since I firmly believe that skipping it and expecting linear results with real transistors is like pushing a panel upstream from the trailing edge), for instance if a 100mV dynamic error range is desired, 100ohms of degen would be needed if the DCOP is 1mA. If I am anywhere near grasping this, I can see that decreasing the DCOP increases the relative noise thus, right?
-By the way I am definitely interested in all OBJECTIVE input regarding resistor technology choice (metal film, carbon, etc.) relative to noise contribution... Using a brute-force technology basis to minimize noise is more elegant IMO than using calculations/optimizations to minimize noise, like exercising and avoiding saturated fat in your diet instead of eventually having liposuction to get a date. For instance, if I know that carbon resistors are the most noisy I simply will not use them in my builds. I am quite skeptical of what I might hear about this however since the equation for J-N noise only includes the resistance value, bandwidth of concern, absolute temperature, and the Boltzmann CONSTANT. I am open to the notion that in an intrinsic 'differential element' view (the space integral of which represents an entire resistor), resistors (like everything else in the real world) may present spatial discretization issues apart from classic parasitics, which would open the door for technology to have an influence on this, arising from various components of isotropy since no resistor is of infinitesimal size.
(3) Heat dissipation is an obvious issue at "high" currents, where any given (Vce * Ic) product approaches ratings.
(4) It intuitively seems that linearity may suffer at "low" currents. I understand that theoretical OL gain may be increased (whether or not it is desirable) at low currents with other parameters fixed, but I also guess that linearity may suffer as devices are operated at miniscule proportions of their design, if only by reducing relative effects of any fixed-value degeneration in use. Clearly this must also consider the Hfe factor(s) to not allow quiescent currents to encounter impotence against interstage loading if drive currents relatively approach quiescent tail currents.
Clearly an optimum is suggested; low enough to survive years of dissipation (particularly if you are like me and think it's better to leave your gear energized to specification as continuously as possible for its service lifetime), while high enough to sound nice. So far I have simply referred to as many similar designs as possible to drive or at least suggest my settings with some success (most of which seem to be between 1mA and 5mA in the LTP(s)), but I'd like to learn more about this matter that is probably more critical than indicated by most discussions which are focused on other general principles.
Are there still factors I have yet failed to mention?
Rs.
the input stage sees the Rs while the stage is operating.
The current flowing through that Rs generates current noise.
If Rs is high then for low noise the current must be low (input bias current).
And similarly if Rs is low then higher currents can be tolerated for low noise operation.
Looking at the input pair parameters and, if given, the noise graphs, you will see that collector current determines input bias current and this input current from Rs determines how much current noise is generated. Even noisy transistors will seem to be quiet when Rs is <1r0.
hFE and transistor construction control this.
Now to voltage noise. I think (note think!) this is determined by the emitter current and the degeneration resistor if fitted. Let's hear more.
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