Dear All:
I just got my 45Mhz XO and a 74HC74 chip to build a divided by 2 circuit as below to get 22.5Mhz frequency, but I'm unable to get DAC lock to in coming SPDIF, while Pin 6 got 3.3V out
http://www.tentlabs.com/Components/XO/assets/Divide by 2.pdf
Vcc to Pin 1, 4, 14
GND to Pin 7, Pin 10-13
Frequency IN at Pin 3
D and Q short together as Pin 2 and Pin 5
Pin 6, 8, 9 - not connected
I have no oscilloscope to see the waveform, only got multimeter, to check, do I make anything wrong?? any advise, input and referral to previous discussion are welcome!
I just got my 45Mhz XO and a 74HC74 chip to build a divided by 2 circuit as below to get 22.5Mhz frequency, but I'm unable to get DAC lock to in coming SPDIF, while Pin 6 got 3.3V out
http://www.tentlabs.com/Components/XO/assets/Divide by 2.pdf
Vcc to Pin 1, 4, 14
GND to Pin 7, Pin 10-13
Frequency IN at Pin 3
D and Q short together as Pin 2 and Pin 5
Pin 6, 8, 9 - not connected
I have no oscilloscope to see the waveform, only got multimeter, to check, do I make anything wrong?? any advise, input and referral to previous discussion are welcome!
Multiply by 2 clock?
I am glad that works as I have been studyuing that circuit too.
Bit off topic, just curious, is it possible to multiply a clock by 2 as well? Say to achieve 22.5 from a 11.2 clock. I can understand there will be more jitter on the line, but I wonder if it is possible so it can be sent to say a clock in the transport (Juli@ soundcard to be specific) as an external master clock from the 11.2 superclock in my tda1541a dac. As the data will be reclocked again in the dac it may not matter if this 22.5 is a bit 'dirty' as well.
Thanks
Regards
Fib
I am glad that works as I have been studyuing that circuit too.
Bit off topic, just curious, is it possible to multiply a clock by 2 as well? Say to achieve 22.5 from a 11.2 clock. I can understand there will be more jitter on the line, but I wonder if it is possible so it can be sent to say a clock in the transport (Juli@ soundcard to be specific) as an external master clock from the 11.2 superclock in my tda1541a dac. As the data will be reclocked again in the dac it may not matter if this 22.5 is a bit 'dirty' as well.
Thanks
Regards
Fib
It is possible.
Use an edge(both) detector followed by a monoshot.
However, output will not have 50% duty cycle.
Gajanan Phadte
Use an edge(both) detector followed by a monoshot.
However, output will not have 50% duty cycle.
Gajanan Phadte
Cascaded resonant circuits (tuned to the desired harmonic) with inverters used as amplifiers are commonly used cheaper consumer gear. (Sony XB-770 multiplies 11MHz clock by 3 to 33MHz clock required for the dsd decoder for example.) Works fairly well with odd multiples of the clock frequencies.
PLLs are also commonly used and with the proper divider inside the feedback loop can synthesize a fairly wide range of clock frequencies.
PLLs are also commonly used and with the proper divider inside the feedback loop can synthesize a fairly wide range of clock frequencies.
- Status
- Not open for further replies.