FPGA + WM8741 and jitter

Hi,

I was thinking about driving the PCM input of a WM8741 DAC using the digital output lines of an FPGA based boarb.

The FPGA board has a shared FIFO memory with an embedded uC, so the uC load the wav data from a file to the FIFO memory and the FPGA convert them to PCM format and drive the WM8741 DAC.

I was just wondering about how good the digital signal from the FPGA is in terms of jitter. The oscillator on the FPGA board is 100ppm so I am worried this is not enough stable to guarantee a good sound.

Somebody has some tips/feedback about the architecture?

Do you think it would it be better to modify the board using a high precision oscillator?

Thank you
Marco
 
Clock jitter depends on how the clocks are generated in the FPGA. These are additive to jitter of incoming clocks. The datasheets of the FPGA will have all the jitter specification.

No matter how you optimize, FPGA people will tell you that the minimum jitter in an FPGA is in the order of 100 psec of period jitter (which is the equivalent of 10-15 psec of phase jitter)

I'll say, don't worry about it. Improving the jitter coming out of a reasonable well designed FPGA will require a more sophisticate approach, for example Ian's FIFO reclocking board.