Folded cascode question

Not being an electrical engineer by training, there are pretty big gaps in my circuit knowledge. I'm sure many people here are the same way, having learned basic electronics by staring at enough amplifier circuits.

One particular circuit that always eluded my reasoning is the folded cascode circuit. Would someone care to explain this basic circuit building block? Thanks...Won
If we start of with a common emitter stage designed around a npn transistor (2n3904) you have three parasitic caps.

between CE
between BE
between BC

BE is ~ 8pF
BC is ~ 4pF

But in a common emitterstage BC is multiplyed by the voltagegain.

If your gain is around 100 times your source will see 8pF(BE) + 400pF(BC*voltage gain).

With a cascode or folded cascode the collector voltage only changes few millivolt on lower transistor. So your source will only see 8pF + 4pF.

You will also get a faster stage because of the smaller capacitive load of stage before this one.

That is the short story!

Try Borbeley Audio's homepage. He has some papers on this subject with JFET instead. But it have the same effect on them.

Sonny, I knew what the cascode/folded-cascode did and why it was useful. Sorry, I should've been more specific.

My question was how to implement one, or use one in an amplifier circuit. The cascode is easy, because all you need is to stack some transistors, but there's a trick in the "folding" that I can't quite figure out from what I've seen.

Thanks, Won