I am also interested in LM6172. I have always thought that is just a double LM6171, but now realize they actually do show different behaviours in the datasheets.
Christer,
Have you checked at national.com? The following site implies that they are there:
http://homepages.which.net/~paul.hills/Circuits/Spice/ModelIndex.html
That site has links to over 20,000 spice models.
Good luck!
- Tom Gootee
http://www.fullnet.com/~tomg/index.html
Have you checked at national.com? The following site implies that they are there:
http://homepages.which.net/~paul.hills/Circuits/Spice/ModelIndex.html
That site has links to over 20,000 spice models.
Good luck!
- Tom Gootee
http://www.fullnet.com/~tomg/index.html
You need to remember the Sackinger paper relation
“A General Relationship Between Amplifier Parameters, And Its Application to PSRR Improvement” E Sackinger, J Groette, W Guggenbuhl, IEEE Trans CAS vol 38, #10 10/83 pp 1171-1181
http://citeseer.ist.psu.edu/432448.html
which gives:
1/(CMRR) + 1/(PSRR+) + 1/(PSRR-) = (1/Adiff) * Zload/(Zload+Zout)
as a fundamental relationship for the standard op amp
then you can look at the LM6171 data sheet psrr and cmrr curves and be very confident that the LF pole is just under 10 KHz, also consistent with open loop large signal gain spec of 90 dB
I doubt the measurements are really accurate at 100 MHz, certainly hugely affected by test fixture parasitics
For audio applications you may be able to make the circuit insensitive to the details of the >10MHz reponse
using higher gains which keep loop gain intercept in the 90 degree phase shift region are easiest
decoupling the output from Cload with lossy ferrite or resistor
using noise gain comp if you need audio freq unity gain
National's LM6171A spice model seems to be broadly reasonable on frequency response vs data sheet
“A General Relationship Between Amplifier Parameters, And Its Application to PSRR Improvement” E Sackinger, J Groette, W Guggenbuhl, IEEE Trans CAS vol 38, #10 10/83 pp 1171-1181
http://citeseer.ist.psu.edu/432448.html
which gives:
1/(CMRR) + 1/(PSRR+) + 1/(PSRR-) = (1/Adiff) * Zload/(Zload+Zout)
as a fundamental relationship for the standard op amp
then you can look at the LM6171 data sheet psrr and cmrr curves and be very confident that the LF pole is just under 10 KHz, also consistent with open loop large signal gain spec of 90 dB
I doubt the measurements are really accurate at 100 MHz, certainly hugely affected by test fixture parasitics
For audio applications you may be able to make the circuit insensitive to the details of the >10MHz reponse
using higher gains which keep loop gain intercept in the 90 degree phase shift region are easiest
decoupling the output from Cload with lossy ferrite or resistor
using noise gain comp if you need audio freq unity gain
National's LM6171A spice model seems to be broadly reasonable on frequency response vs data sheet
Tom,
Thanks. I did search Nationals site, without success. The link you provided told where to look, though, so I found the models.
Jcx,
Thanks, I wasn't aware of that relation. I had a strong suspicion, though, that the pole in the PSRR and CMRR curves would coincide with the dominant pole.
In this case it is not an audio application, but higher frequencies, which is why I bother about the higher frequency poles and zeroes. I'll check out the National models, now that I've found them.
Thanks. I did search Nationals site, without success. The link you provided told where to look, though, so I found the models.
Jcx,
Thanks, I wasn't aware of that relation. I had a strong suspicion, though, that the pole in the PSRR and CMRR curves would coincide with the dominant pole.
In this case it is not an audio application, but higher frequencies, which is why I bother about the higher frequency poles and zeroes. I'll check out the National models, now that I've found them.
Here's a link to the Agilent Vendor Spice List
http://eesof.tm.agilent.com/docs/adsdoc2005A/pdf/vcap.pdf
http://eesof.tm.agilent.com/docs/adsdoc2005A/pdf/vcap.pdf
I have searched the net and this forum, but am still looking for the following spice models:
2SC3421 / 2SA1358 (Toshiba)
2SJ201 / 2SK1530 (Toshiba)
2SC3264 / 2SA1295 (Sanken)
Appreciate any help.
Thanks in advance.
Franklin
2SC3421 / 2SA1358 (Toshiba)
2SJ201 / 2SK1530 (Toshiba)
2SC3264 / 2SA1295 (Sanken)
Appreciate any help.
Thanks in advance.
Franklin
I'm dredging up this old thread in order to provide some models. It seems like the best place as some of the models I'm working on are for the 2SA1930/2SC5171 pair and this thread is an early hit in google if you search for 2SC5171 spice model.
Anyway, the models I'm working on are for:
2SA1930
2SC5171
2SA2040
2SC5707
D44H11
D45H11
Thus far I have taken a lot of measurements and used engauge digitizer to extract data from datasheets. I am using information from Bob Cordell's excellent book to help build the models.
Thus far I have a model for the 2SC5707; the others will follow shortly. I'm happy with the Ic vs Vbe, Ic vs Vce, Ceb vs Veb and Ccb vs Vcb matches, less so with hFE vs Ic and fT vs Ic. For these last two, as far as I can tell it's impossible to match these characteristics with the model that spice uses, but if anyone can make these match better without upsetting other things*, that would be appreciated.
*with fT vs Ic, fT at low Ic could fit better if the CJE, VJE and MJE parameters were altered, but this would upset the (currently perfect) match between model and measured Ceb vs Veb.
Here is a ZIP file, containing the models (currently just one model but will be updated with further models as they become available), measurements, data sheets, and LTspice schematic files for evaluating the models.
Anyway, the models I'm working on are for:
2SA1930
2SC5171
2SA2040
2SC5707
D44H11
D45H11
Thus far I have taken a lot of measurements and used engauge digitizer to extract data from datasheets. I am using information from Bob Cordell's excellent book to help build the models.
Thus far I have a model for the 2SC5707; the others will follow shortly. I'm happy with the Ic vs Vbe, Ic vs Vce, Ceb vs Veb and Ccb vs Vcb matches, less so with hFE vs Ic and fT vs Ic. For these last two, as far as I can tell it's impossible to match these characteristics with the model that spice uses, but if anyone can make these match better without upsetting other things*, that would be appreciated.
*with fT vs Ic, fT at low Ic could fit better if the CJE, VJE and MJE parameters were altered, but this would upset the (currently perfect) match between model and measured Ceb vs Veb.
Here is a ZIP file, containing the models (currently just one model but will be updated with further models as they become available), measurements, data sheets, and LTspice schematic files for evaluating the models.
Have you tried taking the data from the digitizer and running it through Eureqa? The set of equations and coefficients obtained can be broken into their components. It's not elegant, but makes a pretty good approximation.
I did this a while back with Eurequa for "hollow state" tetrodes. There are other solver packages, but Eurequa is the on I'm most familiar with (and it's free.)
Thanks for the tip. Had never heard of Eureqa but it looks excellent! However, I'm not sure how it helps in this case? I don't have any control over how spice models transistors - if Eureqa tells me beta vs Ic can be modelled with a fifth-order poly or something there's nothing I can do! I was wondering if maybe there are some more BJT parameters I could add that might help, or maybe I've just made a boo-boo.
What I'm looking for is for hFE vs Ic and fT vs Ic to fit the measured data better!
Hmmm, maybe I'll try playing with Xcjc and see what that does. MJS and CJS are related to the capacitance from collector to substrate; these are discrete transistors so they don't have a substrate like transistors found in integrated circuits.
I suppose in a way they can, not neccesarily substrate but also the package format, ie the capacitance increases when a TO92 device gets put into T0126 package.
Wai-Kai Chen author of various books on analog design suggests the use of these parameters for such. I personally dont use them, Xcjc should be enough to get reasonable results although I havent seen all the parameters youve used yet on your model.
Wai-Kai Chen author of various books on analog design suggests the use of these parameters for such. I personally dont use them, Xcjc should be enough to get reasonable results although I havent seen all the parameters youve used yet on your model.
So, I tried XCJC = 0.5: no change to fT curves 🙁
Then I tried adding CJS = 200pF: no change to fT curves 🙁
On the hFE vs. Ic front, this could be improved by removing the IKF parameter, and using a subcircuit model for the bjt that includes a current-controlled current source from base to emitter, whose current depends on collector current and whose function is extracted from the measured hFE vs Ic curve. Can you have current-controlled current sources in subcircuit models?
I really don't see how to improve the fT vs Ic curves without upsetting the current perfect match between measured and simulated terminal capacitances 🙁
Then I tried adding CJS = 200pF: no change to fT curves 🙁
On the hFE vs. Ic front, this could be improved by removing the IKF parameter, and using a subcircuit model for the bjt that includes a current-controlled current source from base to emitter, whose current depends on collector current and whose function is extracted from the measured hFE vs Ic curve. Can you have current-controlled current sources in subcircuit models?
I really don't see how to improve the fT vs Ic curves without upsetting the current perfect match between measured and simulated terminal capacitances 🙁
Guys, there is a lot of talk about making models, but to my knowledge actually very few such models. You guys talk about parameters and stuff but where's the beef? Have you actually made models or are you just pretending?
If I've just been out of the loop I'd really appreciate pointers to good models I haven't already included in the attached file.
Meanwhile, here is the pittance of mostly reasonable models I've collected. You will find 2SC5171/A1930 models created by Syn08. These were created after measuring the parameters from real devices. You cannot make realistic models for these transistors with the data available from the datasheet. All other models I've found have Cje way too low.
If you have or know of better models than these then please share them. It would be great to have a single library like this one containing all the DIYAudio-approved models.
Harry, I wonder if there are parameters LTSpice just ignores. Maybe they are called something else or you need to use the VBIC mnemonics instead?
What about the quasi-saturation parameters?
What about thermal modelling?
If I could find a schematic-level description of the VBIC or whatever model is in style right now, I would try and create a SPICE macromodel so LTSpice's non-support of self-heating could be circumvented.
If I've just been out of the loop I'd really appreciate pointers to good models I haven't already included in the attached file.
Meanwhile, here is the pittance of mostly reasonable models I've collected. You will find 2SC5171/A1930 models created by Syn08. These were created after measuring the parameters from real devices. You cannot make realistic models for these transistors with the data available from the datasheet. All other models I've found have Cje way too low.
If you have or know of better models than these then please share them. It would be great to have a single library like this one containing all the DIYAudio-approved models.
Harry, I wonder if there are parameters LTSpice just ignores. Maybe they are called something else or you need to use the VBIC mnemonics instead?
What about the quasi-saturation parameters?
What about thermal modelling?
If I could find a schematic-level description of the VBIC or whatever model is in style right now, I would try and create a SPICE macromodel so LTSpice's non-support of self-heating could be circumvented.
Thanks for your message. If you go back to post #47 you will see that I mentioned that I have taken lots of measurements myself as well as extracting data from datasheets. Everything I have is contained in the linked zip file.
I've just finished constructing a model for the 2SC5171 (not in the zip file yet); I'll compare syn08's version to mine.
I sometimes just tweak some models a little, have done so with some of Cordells models but they are in fact very good.
The Cje parameter creates some difficulties, to tweak Ft at high IC it needs to be made lower than actual measurement but at low IC the opposite is needed.
Some other parameter is needed to define ft better.
I gave up as I dont have the time but youre probably right that LTSpice is not programed for some parameters. Something to look into.
keantoken, I had a look at syn08's 2SC5171 model; it is not good.
Whilst it did fit beta vs Ic better than my model, in every other respect (Ic vs Vbe, fT vs Ic, Ic vs Vce, Ccb and Ceb) the match between model and datasheet/measured values was poor or very poor.
I have "completed" my models for the following:
2SC5171
2SA1930
D44H11
D45H11
I have removed the 2SC5707 model because it's not up to scratch (yet); I don't have time at the moment to fix it but will do eventually.
The link to the zip is the same; the zip includes Excel files which graph measured/datasheet values and those achieved by the spice models.
It would seem that for transistors that have a very flat beta vs Ic over a few decades of Ic and then a sudden drop cannot be modelled by a simple Spice model. My compromise is to keep beta pretty flat and bear in mind when simulating that beta at high Ic will be overly optimistic in the Spice model. It's possible to get a "better" fit (read: lower rms error over the Ic current range) of beta vs. Ic, by allowing some curvature in the characteristic at low Ic, and making "aggressive" use of the parameter "NK" (not mentioned in Bob's book and not documented in LTspice). However, this leads to greater error in beta at low currents where the real device is flat vs Ic, and also to significant errors in the Ic vs Vbe curve at higher currents. The error in the latter curve can be reduced by using the RBM and IRB parameters, but can't be anywhere close to eliminated because the way RB is varied by RBM/IRB doesn't map well to how beta is being varied by IKF and NK.
I did discover that it was possible to increase CJE without too greatly affecting simulated Cbe vs Veb and I have therefore been able to model fT vs Ic at low currents much more accurately. fT at high Ic is still an issue if in the real device it drops-off very suddenly (e.g. the 2SC5707), and also fT at low Vce can be problematic.
As I was trying to improve the models I discovered a series of posts by andy_c, here. I downloaded his spreadsheet and also had a look at his website. I made some minor tweaks to his spreadsheet and used this to help determine the model parameters for optimum Ic vs vbe and beta vs Ic. The modified spreadsheet is available in my zip file.
andy_c's original spreadsheet also had sheets for matching ft vs Ic, but he notes on his website that these use an incorrect method for calculating fT. I did not have time to investigate the proper method, and I also had issues with the parameter "FC" not behaving in the manner I expected. andy_c notes on his website that using the parameter "FC" it should be possible to match fT at high Ic better, and that using a more advanced model for transistor saturation should help with fT at low Vce. Unfortunately I don't have the time right now to research this further.
With all of that said, I now have models that I'm happy to use; whilst not perfect they're a heck of a lot better than nothing! Maybe one day I'll have time to look into this further.
Does anyone have andy_c's contact details? If so please PM me; I would like to thank him personally for his forum posts, spreadsheet and website as they have all been most helpful.
Whilst it did fit beta vs Ic better than my model, in every other respect (Ic vs Vbe, fT vs Ic, Ic vs Vce, Ccb and Ceb) the match between model and datasheet/measured values was poor or very poor.
I have "completed" my models for the following:
2SC5171
2SA1930
D44H11
D45H11
I have removed the 2SC5707 model because it's not up to scratch (yet); I don't have time at the moment to fix it but will do eventually.
The link to the zip is the same; the zip includes Excel files which graph measured/datasheet values and those achieved by the spice models.
It would seem that for transistors that have a very flat beta vs Ic over a few decades of Ic and then a sudden drop cannot be modelled by a simple Spice model. My compromise is to keep beta pretty flat and bear in mind when simulating that beta at high Ic will be overly optimistic in the Spice model. It's possible to get a "better" fit (read: lower rms error over the Ic current range) of beta vs. Ic, by allowing some curvature in the characteristic at low Ic, and making "aggressive" use of the parameter "NK" (not mentioned in Bob's book and not documented in LTspice). However, this leads to greater error in beta at low currents where the real device is flat vs Ic, and also to significant errors in the Ic vs Vbe curve at higher currents. The error in the latter curve can be reduced by using the RBM and IRB parameters, but can't be anywhere close to eliminated because the way RB is varied by RBM/IRB doesn't map well to how beta is being varied by IKF and NK.
I did discover that it was possible to increase CJE without too greatly affecting simulated Cbe vs Veb and I have therefore been able to model fT vs Ic at low currents much more accurately. fT at high Ic is still an issue if in the real device it drops-off very suddenly (e.g. the 2SC5707), and also fT at low Vce can be problematic.
As I was trying to improve the models I discovered a series of posts by andy_c, here. I downloaded his spreadsheet and also had a look at his website. I made some minor tweaks to his spreadsheet and used this to help determine the model parameters for optimum Ic vs vbe and beta vs Ic. The modified spreadsheet is available in my zip file.
andy_c's original spreadsheet also had sheets for matching ft vs Ic, but he notes on his website that these use an incorrect method for calculating fT. I did not have time to investigate the proper method, and I also had issues with the parameter "FC" not behaving in the manner I expected. andy_c notes on his website that using the parameter "FC" it should be possible to match fT at high Ic better, and that using a more advanced model for transistor saturation should help with fT at low Vce. Unfortunately I don't have the time right now to research this further.
With all of that said, I now have models that I'm happy to use; whilst not perfect they're a heck of a lot better than nothing! Maybe one day I'll have time to look into this further.
Does anyone have andy_c's contact details? If so please PM me; I would like to thank him personally for his forum posts, spreadsheet and website as they have all been most helpful.