Hi,
Guido Tent adviced on another topic to send directly a low jitter clock to the DAC for the BCK signal, instead of using the BCK from the decoder/filter.
http://www.diyaudio.com/forums/showthread.php?s=&threadid=51464&highlight=
This, for sure, will give a much cleaner clock to the DAC.
But what about non oversampling DACs?
For an I2S configuration, with a 11.2Mhz clock, tell me if I'm wrong but the BCK out of the decoder will be 2.8MHz (master clock/4)
So, in a NON-OS configuration, how can we feed the DAC with this "direct clock". A solution would be to divide the master clock per 4 (with a counter or 2 D flip flops), but a problem seems to exist with this solution: we don't know "where" to divide the clock.
I don't know if this explanation is clear, but the clock/4 can have 4 differents "phases" or "delays", it can have it's rising edge on the 1st, the 2nd, the 3rd or the 4th edge of the master clock.
And if this divided clock doesn't have the edges at the right time (at the same time that the BCK outputted from the decoder) I think that nothing will work.
Any ideas?
Guido Tent adviced on another topic to send directly a low jitter clock to the DAC for the BCK signal, instead of using the BCK from the decoder/filter.
http://www.diyaudio.com/forums/showthread.php?s=&threadid=51464&highlight=
This, for sure, will give a much cleaner clock to the DAC.
But what about non oversampling DACs?
For an I2S configuration, with a 11.2Mhz clock, tell me if I'm wrong but the BCK out of the decoder will be 2.8MHz (master clock/4)
So, in a NON-OS configuration, how can we feed the DAC with this "direct clock". A solution would be to divide the master clock per 4 (with a counter or 2 D flip flops), but a problem seems to exist with this solution: we don't know "where" to divide the clock.
I don't know if this explanation is clear, but the clock/4 can have 4 differents "phases" or "delays", it can have it's rising edge on the 1st, the 2nd, the 3rd or the 4th edge of the master clock.
And if this divided clock doesn't have the edges at the right time (at the same time that the BCK outputted from the decoder) I think that nothing will work.
Any ideas?
Bricolo said:
I don't know if this explanation is clear, but the clock/4 can have 4 differents "phases" or "delays", it can have it's rising edge on the 1st, the 2nd, the 3rd or the 4th edge of the master clock.
And if this divided clock doesn't have the edges at the right time (at the same time that the BCK outputted from the decoder) I think that nothing will work.
Any ideas?
Hi Bricolo
You could use the low jitter clock to re-clock the BCK before feeding it to the DAC.
Re: Re: Feeding the internal DAC's BCK directly with the player's low jitter clock
Spot on !
cheers
Fin said:
Hi Bricolo
You could use the low jitter clock to re-clock the BCK before feeding it to the DAC.
Spot on !
cheers
Bricolo said:yes, I know this would work.
but I wanted to know if the div/4 works or not
Hi
Should work as well, maybe timing spoils it
OK so I'll go for reclocking.
After all, having to divide and to reclock in order to attenuate the counter's jitter isn't easier
After all, having to divide and to reclock in order to attenuate the counter's jitter isn't easier
Bricolo said:OK so I'll go for reclocking.
After all, having to divide and to reclock in order to attenuate the counter's jitter isn't easier
True, reclocking needs only 1 Dff (use low noise power supply here too......)
succes
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