Check your bias voltage at the gate traces for the output fets. You should be able to turn it down to zero with the trimmers. If you cant you have a problem in the board somewhere.
Let me try again, that wasn,t right. Check to see that you can adjust the voltage across R3 and R4 from zero to 5v with the trim pots.
Check your bias voltage at the gate traces for the output fets. You should be able to turn it down to zero with the trimmers. If you cant you have a problem in the board somewhere.
from what to what? with the output FETs in or not?
can you post pictures of your setup?
I put a few pics up here
An externally hosted image should be here but it was not working when we last tested it.
Across R3 and R4. Do you have the schematic? That should be the same voltage you get from the rail to the gate pin of the output fet, which is pin 1. Dont put the fets in until you have this under control.
Let me try again, that wasn,t right. Check to see that you can adjust the voltage across R3 and R4 from zero to 5v with the trim pots.
That works fine
Across R3 and R4. Do you have the schematic? That should be the same voltage you get from the rail to the gate pin of the output fet, which is pin 1. Dont put the fets in until you have this under control.
If Pin 1 is next to the Q3 designation and opposite the Q4 designation, then I have 5v there when I have 5v across r3/r4.
hmmmmm
Looks like I've mixed up the data sheets, had the n channel and p channel mixed up. Dang I hate it when I do that.
I've swapped them but I have the same results.
Q3 is now a Toshiba 2SJ201 P channel, replacing the indicated IRF9240 P Channel
Q4 is now a Toshiba 2SK1530 N Channel, replacing an IRF240 N Channel
I guess I've blown an expensive pair of Toshiba outputs?
I've swapped them but I have the same results.
Q3 is now a Toshiba 2SJ201 P channel, replacing the indicated IRF9240 P Channel
Q4 is now a Toshiba 2SK1530 N Channel, replacing an IRF240 N Channel
I guess I've blown an expensive pair of Toshiba outputs?
There is no reason not to do it now, just for added safety on start up with new fets.
I know how easy it is to mix the fets up when building, I luckily caught it when I built mine.
I know how easy it is to mix the fets up when building, I luckily caught it when I built mine.
Yes, I can adjust the pin 1 pad (outputs out) vs the adjoining rail to 0V with the trim pots, both rails.
Does that mean I'm good to go for trying new FETs?
Do I leave it at 0v to start after the replacement?
Does that mean I'm good to go for trying new FETs?
Do I leave it at 0v to start after the replacement?
Yep, just bring each one up a turn at a time til you get close to correct bias, then fine tune your bias and offset.
Have fun.
Have fun.
Thanks Bill. I appreciate your gentle guidance.
I'm at 608/614 and .007 offset right now. Heatsink is toasty but the fins are facing down instead of vertical so I think I'm gonna be fine.
Except for frying those Toshiba outputs I mean.
I'm at 608/614 and .007 offset right now. Heatsink is toasty but the fins are facing down instead of vertical so I think I'm gonna be fine.
Except for frying those Toshiba outputs I mean.
- Status
- Not open for further replies.
- Home
- Amplifiers
- Pass Labs
- f5 power up issue