F5 bias

[gadut]

24 off 15mF for two channels could be arranged

CRCLCCCC per channel per rail

haha..should I use 2.2mH? more cost for extra caps 🙂 already paid so much for those 12 caps..24 caps will kill my pocket 🙂

got these caps with lower price in local store, around $16.5/pcs
2 X NICHICON KG GOLD TUNE 15000uF 63VDC CAPACITOR!

 

[a.wayne]

24 off 15mF for two channels could be arranged

CRCLCCCC per channel per rail

Why so many caps, why not 12 of 30mf and what size inductor ...?

 

[andRookie]

it's not double current. more like 30% rise.
ripple is 3.59A eatch cap.

It is the rippel voltage on the output of the powersupply he is concerned about. If you download PSUD2 you can model the rippelvoltage and see what happends when the current draw rises.

 

[AndrewT]

nice build, can't wait to start mine 🙂 anyway which one is better configuration, CCCC R CC or CC R CCCC ? but it's for my aleph30 with 2pcs talema 2x18V 225VA and 12pcs 15.000uF, so each channel will be supplied by 90.000uF which already exceeds aleph30 design which is 60.000uF per channel

Because I read this to mean he proposes to use 12 off 15mF per channel.

 

[AndrewT]

Why 2m2H?
what's wrong with the same wire resistance as that first R, try 0r2.

 

[gadut]

Because I read this to mean he proposes to use 12 off 15mF per channel.

Why 2m2H?
what's wrong with the same wire resistance as that first R, try 0r2.

I proposed to use 12 off 15mF for both channel 🙂

I'm using 3x0R3 5W parallel to get 0R1 15W for each R series, and I find that common CLC aleph psu design in kk-pcb use 1.8-2.7mH. so what's your suggestion on L value?

 

[AndrewT]

9m of 1.4mm diam copper gives ~0r1 and when wound 8T/Layer and 9Layers (75.8T) on a 27mm diam spool results in ~0.2mH

Total heat in that coil would be ~300mW @ 1.7Adc

so back to Jacco's suggestion
CRCC or CLCC