Look guys. Do your homework!!
Just one hint to start with:
There is a difference between a "logical" bit and a "physical" - or you might call it "analog" - bit.
If you guys start realizing that there might be a difference between both versions you're on the right track.
Another hint:
Think about what "jitter" is and how it affects the sound...
...Yep, a logical 1 still remains a 1, even with decent jitter in the pipe.
Enjoy.
Bits are bits whatever you say, I would suggest reading all the stuff on signal integrity, that's how we get the data from a to b so that it can be read, jitter is jitter, the data is still bits.... the timing has changed very slightly.
The data is transmitted as a roughly square ware or a digital signal, it is not an analogue signal, it has but two representations when read logical 1 or logical 0 there are no in between bits unlike analogue signals that are time varying.....
Most of you not even involved in signal integrity have to bother about the analogue elements of square waves that what we deal with with signal integrity when doing the layout and interfaces, so that the data is BITS.
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You'll probably find that these days most interfaces are pretty much bit perfect.
Thanks Soundcheck for the links, I will read it. I will start first with the Pi3 I have already and the Moode Audioplayer as I believe Tim made a great job here. But as I'm a curious man, I will check some other boards and distros when I will be less busy. I don't understand how the soft can affect the I2S signal outputt (tcp interface at inputt is buffered and bit perfect as if a datagrame is lost, the missing one is called again )- The isochrnous transfer on the 3 I2S line at the outputt should be wasted by a soft with a less good development???I don't understand (In my case the i2S signals are buffered in a Fifo after the Pi3 then time re synchronised in relation to each others by a more precise clock which is isolated from the noise than the Pi3 could inject if I understood the concept of IanCanada devices I have : I2S signal restart from the same precise timing window with a quiet clock- btw where the noise is acting here in this still digital domain???)
@ Marce : Hi Marce, may you please fatly explain to me how the noise of a PS has can change the sound when feeding the pcbs and components of a board which are only involved by a digital signal ? is there an overlapping of noise above the digital signal : datas stay good but the noise is transmitted after the conversion to the analog stage ? Or does it affect only the timing channel of our I2S ?
By the way in a digital streaming how is the signal ? on-off for 1-0, so a pulse ? or a continuous signal with lower and higher modulation to translate the digital zero or one ? (I'm ashamed to ask I learned that for IT 15 years ago but forgott ... I never used it in networks administration as a final user !)!
Well I receive my LiPoFe4 to feed the clock board which is after a FIFO with an isolator (chip) in between ! Maybe good cells with very low ESR are not better for all of that... Hard to understand where is the noise between the electrical signal and the logical one for a newbie !
I planned the big LiPo tankcell for the Pi3 : goal : free of noise in relation to a wall plug ! The Fifo will be feeded from this cell from the Pi.
Then after the isolator, the clock board with Crystek XOs feeded by a A123 LiPoFe4 cell (the ESR of this cell is lower than the main SMD cap that feeds the reg on the reclock board...
Am I going too far ????? Some noticed huge difference this way as Supra member from Australia with the same setup as I have...
@ Marce : Hi Marce, may you please fatly explain to me how the noise of a PS has can change the sound when feeding the pcbs and components of a board which are only involved by a digital signal ? is there an overlapping of noise above the digital signal : datas stay good but the noise is transmitted after the conversion to the analog stage ? Or does it affect only the timing channel of our I2S ?
By the way in a digital streaming how is the signal ? on-off for 1-0, so a pulse ? or a continuous signal with lower and higher modulation to translate the digital zero or one ? (I'm ashamed to ask I learned that for IT 15 years ago but forgott ... I never used it in networks administration as a final user !)!
Well I receive my LiPoFe4 to feed the clock board which is after a FIFO with an isolator (chip) in between ! Maybe good cells with very low ESR are not better for all of that... Hard to understand where is the noise between the electrical signal and the logical one for a newbie !
I planned the big LiPo tankcell for the Pi3 : goal : free of noise in relation to a wall plug ! The Fifo will be feeded from this cell from the Pi.
Then after the isolator, the clock board with Crystek XOs feeded by a A123 LiPoFe4 cell (the ESR of this cell is lower than the main SMD cap that feeds the reg on the reclock board...
Am I going too far ????? Some noticed huge difference this way as Supra member from Australia with the same setup as I have...
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Near as I can tell, the only real reason to choose an RPi2 over a RPi3 at this point is the theoretical power consumption advantage for the 2, which should still be put into perspective of overall system power consumption - 50% higher is a big deal when its 50% of the system power budget, rather less so when it is 5%. Price could, theoretically, be an advantage for the RPi2, but retailers seem to be selling it at the same price as the 3.
The Pi2 might also have greater maturity on the software side, but the Pi3 is surely attracting more and more of the communities attention.
In the end, while we might have hoped that the 3 had better high-speed I/O, or more memory, or what have you, it is, in almost every dimension, a more capable device than the 2, and in ways that many if not most users will experience.
It's faster in benchmarks of most things, except for the frustrating I/O. It includes WiFi and Bluetooth, which will be an improvement for many applications.
It will likely grow faster still in some areas, when Raspbapian, or your distribution of choice embraces AArch64.
The Pi2 might also have greater maturity on the software side, but the Pi3 is surely attracting more and more of the communities attention.
In the end, while we might have hoped that the 3 had better high-speed I/O, or more memory, or what have you, it is, in almost every dimension, a more capable device than the 2, and in ways that many if not most users will experience.
It's faster in benchmarks of most things, except for the frustrating I/O. It includes WiFi and Bluetooth, which will be an improvement for many applications.
It will likely grow faster still in some areas, when Raspbapian, or your distribution of choice embraces AArch64.
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