Correction...aargh!
Christer,
You are right, this is my error. I wrote "IKF" when I should have written "ITF". In post number 18 I mention "adjusting CJE, TF and ITF to try to match the data sheet's ft vs Ic as closely as possible", which is corrrect. You can see the ITF value I use for the MJL3281A has been adjusted to a different value from the On Semiconductor model.
Sorry for the confusion! And thanks for catching the error.
I haven't tried to go back and readjust the DC characteristics of the MJL3281A with regard to beta falloff at high currents in order to better match the ft vs Ic curves at high currents though.
Regarding saturation, I don't think SPICE models this particularly well, but I haven't gone into detail as I have with the ft vs. Ic stuff. I don't see the importance of this for the study of crossover distortion, since the output devices are either in the active region or cutoff for a normal amp. Driving them into saturation would require forward biasing the collector-base junction, which in turn requires the drive voltage to the base to exceed the supply. In the case of the simulation I did in the other thread, I just used an input voltage of 0+/-5V with a +/-56 Volt supply.
Christer said:
Christer,
You are right, this is my error. I wrote "IKF" when I should have written "ITF". In post number 18 I mention "adjusting CJE, TF and ITF to try to match the data sheet's ft vs Ic as closely as possible", which is corrrect. You can see the ITF value I use for the MJL3281A has been adjusted to a different value from the On Semiconductor model.
Sorry for the confusion! And thanks for catching the error.
I haven't tried to go back and readjust the DC characteristics of the MJL3281A with regard to beta falloff at high currents in order to better match the ft vs Ic curves at high currents though.
Regarding saturation, I don't think SPICE models this particularly well, but I haven't gone into detail as I have with the ft vs. Ic stuff. I don't see the importance of this for the study of crossover distortion, since the output devices are either in the active region or cutoff for a normal amp. Driving them into saturation would require forward biasing the collector-base junction, which in turn requires the drive voltage to the base to exceed the supply. In the case of the simulation I did in the other thread, I just used an input voltage of 0+/-5V with a +/-56 Volt supply.
OK, that clears up things. ITF is also one of the newer parameters
for which I have no equations in my books. Do you know
anything about how it affects the behaviour and/or what
the value denotes?
Sorry about the crossover distorsion. I realized later that I was
wrong, but was away from the computer then.
for which I have no equations in my books. Do you know
anything about how it affects the behaviour and/or what
the value denotes?
Sorry about the crossover distorsion. I realized later that I was
wrong, but was away from the computer then.
I'll get the relevant equations for you from Massobrio and Antognetti. I could easily get them wrong since I don't have them memorized 😉. The book is at home and I'm at work now, so when I get back I'll look them up and post at least the highlights of the equations for you.
Okay, here's the relevant text from Massobrio and Antognetti:
"At high currents, ft and TF become a function of Ic and Vce and do not remain constant. Physically, anomalies such as base pushout, lateral spreading, space-charge-limited current flow, and quasi-saturation increase the transit time and decrease ft. This effect is modeled by the following empirical function:
ATF=1+XTF*(Icc/(Icc+ITF))^2*exp(Vbc/(1.44*VTF))
"This function multiplies TF in the charge equations. The constant 1.44 simply gives the interpretation to VTF as the value of Vbc where the exponential equals 1/2. XTF (a SPICE2 parameter) controls the total fall-off of ft; VTF (a SPICE2 parameter) dominates the change in ft with respect to Vce; ITF (a SPICE2 parameter) dominates the change in ft with respect to current."
Looking at the capacitance equations, it's a bit confusing because they split into a number of different regions of Vbe, and it's not clear which region applies to a specific case. But one of the terms of Cbe looks like:
Cbe = TF*q*Is/(k*T)*exp(q*Vbe/(k*T)) + ...
So it's at least semi-clear that the scaling of TF makes Cbe bigger, thus reducing ft at high currents. I found that there were a large number of combinations of XTF and ITF that gave essentially the same results. So for the MJL3281a, I kept XTF at the value supplied by On Semiconductor, and varied ITF to fit ft vs Ic at high currents. The value of ITF I used had no effect on ft below 1A for the MJL3281a. This allowed fitting ft vs Ic at low currents using only TF and CJE.
"At high currents, ft and TF become a function of Ic and Vce and do not remain constant. Physically, anomalies such as base pushout, lateral spreading, space-charge-limited current flow, and quasi-saturation increase the transit time and decrease ft. This effect is modeled by the following empirical function:
ATF=1+XTF*(Icc/(Icc+ITF))^2*exp(Vbc/(1.44*VTF))
"This function multiplies TF in the charge equations. The constant 1.44 simply gives the interpretation to VTF as the value of Vbc where the exponential equals 1/2. XTF (a SPICE2 parameter) controls the total fall-off of ft; VTF (a SPICE2 parameter) dominates the change in ft with respect to Vce; ITF (a SPICE2 parameter) dominates the change in ft with respect to current."
Looking at the capacitance equations, it's a bit confusing because they split into a number of different regions of Vbe, and it's not clear which region applies to a specific case. But one of the terms of Cbe looks like:
Cbe = TF*q*Is/(k*T)*exp(q*Vbe/(k*T)) + ...
So it's at least semi-clear that the scaling of TF makes Cbe bigger, thus reducing ft at high currents. I found that there were a large number of combinations of XTF and ITF that gave essentially the same results. So for the MJL3281a, I kept XTF at the value supplied by On Semiconductor, and varied ITF to fit ft vs Ic at high currents. The value of ITF I used had no effect on ft below 1A for the MJL3281a. This allowed fitting ft vs Ic at low currents using only TF and CJE.
** BUMP **
Hi all,
My first post! I've been searching the web trying to figure out how to generate a "ft vs collector current" chart for the BJT when I stumbled across this thread.
In the first post andy_c outlines the method he uses to generate this chart, but I got slightly confused on the actual details of this process. I understand you use the beta or hfe vs frequency chart to calculate fT, but how do you go from that chart to the ft vs collector current chart?
Alternatively, does anyone know of any books or resources on the web that would give a step by step guide for dummies on how to reproduce this chart?
Regards,
BIC
Hi all,
My first post! I've been searching the web trying to figure out how to generate a "ft vs collector current" chart for the BJT when I stumbled across this thread.
In the first post andy_c outlines the method he uses to generate this chart, but I got slightly confused on the actual details of this process. I understand you use the beta or hfe vs frequency chart to calculate fT, but how do you go from that chart to the ft vs collector current chart?
Alternatively, does anyone know of any books or resources on the web that would give a step by step guide for dummies on how to reproduce this chart?
Regards,
BIC
good job Andy, thanks for your efforts!
I gave up looking at ON Semi's models after a bad experience.
I was told that the models were built to the data sheet. I found that the Early voltage would be pretty poor as it reflects worse case data for leakage current. Transistors usually approach avalanche sort of exponentially and at lower voltages than the 250V breakdown or whatever, they're likely to be much better. I measured my own Early voltages. Much better.
(andy probably knows but in case others don't, you don't need a curve tracer to do that. Only a dual channel oscilloscope or even an adjustable supply, an ammeter, and a hefty heatsink).
cheers
John
I gave up looking at ON Semi's models after a bad experience.
I was told that the models were built to the data sheet. I found that the Early voltage would be pretty poor as it reflects worse case data for leakage current. Transistors usually approach avalanche sort of exponentially and at lower voltages than the 250V breakdown or whatever, they're likely to be much better. I measured my own Early voltages. Much better.
(andy probably knows but in case others don't, you don't need a curve tracer to do that. Only a dual channel oscilloscope or even an adjustable supply, an ammeter, and a hefty heatsink).
cheers
John
andy_c said:
Hi,
This gets at a question I've always wanted to know the answer.
How much non-linear behavior of Cbe and the other capacitance
of a BJT is captured in LTSpice?
DC parameters?
Hi Andy,
I'm taking another look at output stages with gain and decided to use your models under discussion here. Nice work by the way, very nice, and thanks for offering it here.
I'm looking at just the driver and output stage of the old Univeral Tiger, open loop obviously and I'm seeing some strange behavior: http://www.diyaudio.com/forums/showthread.php?threadid=41926
I wanted to try modern faster, higher gain devices such as these. What I'm seeing is what I believe is poor current gain above about Ic=3 amps from the PNP device (Qmjl1302a). The circuit does fairly well at clipping into an 8 ohm load, but grossly lacks symmetry with a 4 ohm load that requires a peak current of 5 amps. I looked at the data sheet for these devices and they seem to track (Vsat, hfe), well up to 8-10 amps or so.
I checked the schematic several times, and finally made an exact compliment to the NPN as a test case and sure enough it was symmetrical.
I'm wondering if you checked the basic DC characteristics of the Qmjl1302a against the data sheet?
I'm aware that NPN and PNP complementary devices are usually quite different, but these are supposed to be well matched devices, and I'm seeing grossly different behavior.
I'm being lazy here, I wanted this to be a quick simulation and I didn't want to spend a lot of time checking out models, so I thought I'd ask you first.
Pete B.
Off topic: Sure would be nice to add EC to this output stage given all the discussion.
Hi Andy,
I'm taking another look at output stages with gain and decided to use your models under discussion here. Nice work by the way, very nice, and thanks for offering it here.
I'm looking at just the driver and output stage of the old Univeral Tiger, open loop obviously and I'm seeing some strange behavior: http://www.diyaudio.com/forums/showthread.php?threadid=41926
I wanted to try modern faster, higher gain devices such as these. What I'm seeing is what I believe is poor current gain above about Ic=3 amps from the PNP device (Qmjl1302a). The circuit does fairly well at clipping into an 8 ohm load, but grossly lacks symmetry with a 4 ohm load that requires a peak current of 5 amps. I looked at the data sheet for these devices and they seem to track (Vsat, hfe), well up to 8-10 amps or so.
I checked the schematic several times, and finally made an exact compliment to the NPN as a test case and sure enough it was symmetrical.
I'm wondering if you checked the basic DC characteristics of the Qmjl1302a against the data sheet?
I'm aware that NPN and PNP complementary devices are usually quite different, but these are supposed to be well matched devices, and I'm seeing grossly different behavior.
I'm being lazy here, I wanted this to be a quick simulation and I didn't want to spend a lot of time checking out models, so I thought I'd ask you first.
Pete B.
Off topic: Sure would be nice to add EC to this output stage given all the discussion.
Re: DC parameters?
Hi Pete,
Well, I've got to admit to some embarassment here. When I posted this originally, my thoughts were that they couldn't possibly have messed up something so basic as the DC parameters.
WRONG!!!
But I did discover and fix this later. My web site has new models that fix the DC problems as well. Just click on my web link and there's some pages that describe the whole story. Or you can go directly to the page here
PB2 said:
Hi Pete,
Well, I've got to admit to some embarassment here. When I posted this originally, my thoughts were that they couldn't possibly have messed up something so basic as the DC parameters.
WRONG!!!
But I did discover and fix this later. My web site has new models that fix the DC problems as well. Just click on my web link and there's some pages that describe the whole story. Or you can go directly to the page here
Let me quickly mention some other things I've learned that make some of the info of my original post obsolete.
For finding the simulated fT using LTSpice, there's a much simpler approach than what I outlined in my original post. In fact, forget what I originally said! To find fT, do the following:
1) Set up a simple bias circuit for the transistor, establishing the Vce and Ic. It doesn't have to be identical to the actual circuit in use, as long as Vce and Ic are the same. I usually ground the base and put a current source in the emitter.
2) Set the simulator to find the operating point.
3) Do a View, SPICE error log.
In the error log, you will find fT computed for you. To find a graph of fT vs. current, it's necessary to repeat (1)-(3) at each current. I don't know of any way to automate this.
For more info, see my web page.
Regarding the base-emitter junction capacitance vs. voltage, this is fully modeled in SPICE. For more details, see my web page in the section about fT vs. current. It also describes the workaround SPICE uses to avoid the singularity in the capacitance vs. voltage that would otherwise occur in the forward-biased region.
For finding the simulated fT using LTSpice, there's a much simpler approach than what I outlined in my original post. In fact, forget what I originally said! To find fT, do the following:
1) Set up a simple bias circuit for the transistor, establishing the Vce and Ic. It doesn't have to be identical to the actual circuit in use, as long as Vce and Ic are the same. I usually ground the base and put a current source in the emitter.
2) Set the simulator to find the operating point.
3) Do a View, SPICE error log.
In the error log, you will find fT computed for you. To find a graph of fT vs. current, it's necessary to repeat (1)-(3) at each current. I don't know of any way to automate this.
For more info, see my web page.
Regarding the base-emitter junction capacitance vs. voltage, this is fully modeled in SPICE. For more details, see my web page in the section about fT vs. current. It also describes the workaround SPICE uses to avoid the singularity in the capacitance vs. voltage that would otherwise occur in the forward-biased region.
Re: Re: DC parameters?
Thanks so much Andy! I find the same thing, every time I think something couldn't possibly be wrong, well think again as they say. I'll check out your site!
Pete B.
andy_c said:
Thanks so much Andy! I find the same thing, every time I think something couldn't possibly be wrong, well think again as they say. I'll check out your site!
Pete B.
I tried the new models - perfect!
Ah, I can sleep better now.
I will read your excellent analysis in detail if I ever have to fix up
some models.
Thanks again,
Pete B.
Ah, I can sleep better now.
I will read your excellent analysis in detail if I ever have to fix up
some models.
Thanks again,
Pete B.
andy_c spreadsheet
Hi Andy,
I'm trying to reproduce your calculations (I want to get better models for the MJL4281 and MJL4302) using your spreadsheet.
My main problem is that, in the spreadsheet you provide, the "Simulated external VBE" and "Simulated IB" are hard coded, i.e. not calculated.
Findind by hand VBE (and the external VBE) as a function of IC is not a trivial task.
I was able to find some result using Mathcad, even if what I get is slightly different from what you state.
The function VBE(IC) depends also on the parameters IS, NF, ISC, VAF, VAR, so I'm trying to understand if even those parameters should be included in the optimization.
Thanks
Hi Andy,
I'm trying to reproduce your calculations (I want to get better models for the MJL4281 and MJL4302) using your spreadsheet.
My main problem is that, in the spreadsheet you provide, the "Simulated external VBE" and "Simulated IB" are hard coded, i.e. not calculated.
Findind by hand VBE (and the external VBE) as a function of IC is not a trivial task.
I was able to find some result using Mathcad, even if what I get is slightly different from what you state.
The function VBE(IC) depends also on the parameters IS, NF, ISC, VAF, VAR, so I'm trying to understand if even those parameters should be included in the optimization.
Thanks
I need to reconsider my question ...
since I didn't take into account all the available data.
Sorry about that.
Thanks
since I didn't take into account all the available data.
Sorry about that.
Thanks
There is an Excel spreadsheet for fitting some of the basic transistor parameters to datasheets available here:
http://www.analogservices.com/excel.htm
I have used it to construct models for some of the Sanken power devices; I haven't checked the Ft vs Ic, but the DC fit for Hfe is not bad, although the high current falloff is more abrupt in the real device than the model.
HTH
http://www.analogservices.com/excel.htm
I have used it to construct models for some of the Sanken power devices; I haven't checked the Ft vs Ic, but the DC fit for Hfe is not bad, although the high current falloff is more abrupt in the real device than the model.
HTH
The on-semi spice models looks not to bad!
Not at this parameter.
Both MJL3281 and MJL1302 Ft vs. Current is reasonable.
Not at this parameter.
Both MJL3281 and MJL1302 Ft vs. Current is reasonable.
Wow, this is an old thread!
The stuff on my web pages regarding the OnSemi models for these devices is out of date now. I originally did those back in Oct. 2006. Since then, they've come out with new models. I haven't looked at those.
Also, there's several other out of date aspects to my web site. The classic Gummel-Poon model as described in Massobrio and Antognetti does not include the effects of quasi-saturation. M&O describe in their book a quasi-sat model that, at the time of writing of the book, was only implemented in HSPICE. However, now LTspice, PSPICE and probably many others use a quasi-sat model originally described in the article:
G. M. Kull, L. W. Nagel, S. W. Lee, P. Lloyd, E. J. Prendergast, and H. K. Dirks, “A Unified Circuit Model for Bipolar Transistors Including Quasi-Saturation Effects,” IEEE Transactions on Electron Devices, ED-32, 1103-1113 (1985).
I'd love to get a copy of this article if anyone has it.
Secondly, when I did that modeling I was new to Excel, having previously only used it for simple financial calculations. Since then, I bought a book on using Visual Basic for Applications (VBA) with Excel. The technique on my web site has many manual steps. This is because I limited my calculations to what could practically be done using formulas in spreadsheet cells. Using VBA, it's possible to automate that process much more than what is shown on my web pages. I'm currently working on some models for the 2sa1837 and 2sc4793 that use this approach.
Going back through the history of this thread, I had plotted hfe vs. frequency to determine fT. This turns out to be unnecessary in LTspice. Using LTspice, one need only do an operating point analysis. The value of fT is then shown in the SPICE error log. This can be combined with the .STEP directive to get many values of fT for a swept IE.
The stuff on my web pages regarding the OnSemi models for these devices is out of date now. I originally did those back in Oct. 2006. Since then, they've come out with new models. I haven't looked at those.
Also, there's several other out of date aspects to my web site. The classic Gummel-Poon model as described in Massobrio and Antognetti does not include the effects of quasi-saturation. M&O describe in their book a quasi-sat model that, at the time of writing of the book, was only implemented in HSPICE. However, now LTspice, PSPICE and probably many others use a quasi-sat model originally described in the article:
G. M. Kull, L. W. Nagel, S. W. Lee, P. Lloyd, E. J. Prendergast, and H. K. Dirks, “A Unified Circuit Model for Bipolar Transistors Including Quasi-Saturation Effects,” IEEE Transactions on Electron Devices, ED-32, 1103-1113 (1985).
I'd love to get a copy of this article if anyone has it.
Secondly, when I did that modeling I was new to Excel, having previously only used it for simple financial calculations. Since then, I bought a book on using Visual Basic for Applications (VBA) with Excel. The technique on my web site has many manual steps. This is because I limited my calculations to what could practically be done using formulas in spreadsheet cells. Using VBA, it's possible to automate that process much more than what is shown on my web pages. I'm currently working on some models for the 2sa1837 and 2sc4793 that use this approach.
Going back through the history of this thread, I had plotted hfe vs. frequency to determine fT. This turns out to be unnecessary in LTspice. Using LTspice, one need only do an operating point analysis. The value of fT is then shown in the SPICE error log. This can be combined with the .STEP directive to get many values of fT for a swept IE.
- Status
- Not open for further replies.