A Japanese technology oriented vendor, Fidelix, provides a board level component.
http://www.fidelix.jp/img/I2S-HDMI.gif
http://www.fidelix.jp/img/I2S-HDMI%20PCB.jpg
The receiver module incorporates an isolator device and its power can be supplied from a transmitter side.
Its price is 15,000 JPY. Their contact address is info@fidelix.jp
Thank you, greatly appreciated. This seems like a great product, but man the price is steep - $ 182!
You can make it yourself based on the schematic. However, soldering around HDMI connector seems very difficult.but man the price is steep - $ 182!
You can make it yourself based on the schematic. However, soldering around HDMI connector seems very difficult.
Yes, you are correct. I am not worried about soldering, did a lots of SMD work, but it is board that is my problem. I never did PCB on my own and without that is difficult.
Question for you engineers: I'm lifting I2S from single circuit board vias and supplying multiple DAC chips. Signal clocks, for example, go from 1 source to 5 different destination chips. It does work to daisy-chain these inputs from one board to the next. Still, is it preferable for each input to originate as close to the source as possible? TIA!
Frank
Frank
Homeruns would be preferable. you actually might want to buffer the signals, since you are paralleling so many sinks.
Thanks Brian! I'll start with short home runs and troubleshoot as necessary after all the I/O is restored... Chassis work seems so mundane after the test-bench setups have been playing beautifully! 😛
Homeruns would be preferable. you actually might want to buffer the signals, since you are paralleling so many sinks.
I would think that buffering would be advisable and necessary but I do not know what is used for buffering of I2S. Could you please elaborate little bit more in detail what is used for this purpose. I know how to do it for S/PDIF but I do not think that same way could be done for I2S.
Thank you.
Thanks Brian! ... and troubleshoot as necessary after all the I/O is restored...
...looked into this a little more. In my case, I see that the source is a Xilinx XC9500 series CPLD. The data sheet is not helpful in forecasting specific drive limitations except to say that pulses should be limited to 200mA and the overall junction temps should be 70C or less even though it is tolerant much hotter. So when I power back up I'll monitor that chip and make sure it is not running hot. I could give it a heatsink! 😀 Also, there are two onboard DACs that I could deactivate. I'm taking considerable care to keep all the I2S lines a minimum length, so my fingers are crossed that a buffer won't be necessary because I don't know where I'd put it.
Hi,
I have one Q
(Maybe Brian is most qualified person to answer...)
I have Sabre dac playing (very good)
in factory settings 80MHz MCL, 24bit, i2S, Ioutput, 50KHz/fast roll-off, jitter reduction
and L/R 4 X DAC ballanced out.
.
My Q is can I set the PIC to SET all DAC units inside to single ended Iout
to one channel?
I want use single chip per channel and I do not need ballanced outs...
?
Thanks
And thankk You Brian for the great great DAC chip
🙂
I have one Q
(Maybe Brian is most qualified person to answer...)
I have Sabre dac playing (very good)
in factory settings 80MHz MCL, 24bit, i2S, Ioutput, 50KHz/fast roll-off, jitter reduction
and L/R 4 X DAC ballanced out.
.
My Q is can I set the PIC to SET all DAC units inside to single ended Iout
to one channel?
I want use single chip per channel and I do not need ballanced outs...
?
Thanks
And thankk You Brian for the great great DAC chip
🙂
And just one q more lplease
:
can I employ 90.3168 MHz master clock with Sabre dac?
( 90.3168 MHz = 4 x 22.5794 MHz = 4 x 512 x 44.1 KHz )
thanks
:
can I employ 90.3168 MHz master clock with Sabre dac?
( 90.3168 MHz = 4 x 22.5794 MHz = 4 x 512 x 44.1 KHz )
thanks
is it a buffalo II? if not you are thanking the wrong guy, brian did not design the sabre chip, only designs that use it
I would think that buffering would be advisable and necessary but I do not know what is used for buffering of I2S. Could you please elaborate little bit more in detail what is used for this purpose. I know how to do it for S/PDIF but I do not think that same way could be done for I2S.
Thank you.
what is needed is actually quite similar. LMV7219 would be fine
Sorry i think about Dustin,
but Brian could help if he know how to?
if He is still around at the topic?
sorry again
but Brian could help if he know how to?
if He is still around at the topic?
sorry again
Hi,
I have one Q
(Maybe Brian is most qualified person to answer...)
I have Sabre dac playing (very good)
in factory settings 80MHz MCL, 24bit, i2S, Ioutput, 50KHz/fast roll-off, jitter reduction
and L/R 4 X DAC ballanced out.
.
My Q is can I set the PIC to SET all DAC units inside to single ended Iout
to one channel?
I want use single chip per channel and I do not need ballanced outs...
?
Thanks
And thankk You Brian for the great great DAC chip
🙂
You can set all DACs with the same phase if that is what you are asking... Take a look at the datasheet...
I went through the sheets,
and i saw the option to switch the phases opposite
BUT
I think that there is no point because
the dac unit (like for the example dac1 to 8
are still ballanced...)
and
turning the phase in mean that You can get only oposite phases
against factory setting...
I simply could not find the information how to split
the + and - Iouts from the single dac unit inside?
Or maybe I get it wrong?
thanks
and i saw the option to switch the phases opposite
BUT
I think that there is no point because
the dac unit (like for the example dac1 to 8
are still ballanced...)
and
turning the phase in mean that You can get only oposite phases
against factory setting...
I simply could not find the information how to split
the + and - Iouts from the single dac unit inside?
Or maybe I get it wrong?
thanks
I need to change the phase of one half of the dac unit
this one "-" to change to "+",
and for every dac unit inside the chip (8 pieces...)
I dont need ballanced line.
🙂
this one "-" to change to "+",
and for every dac unit inside the chip (8 pieces...)
I dont need ballanced line.
🙂
As for ES9018, I have tested 80, 96, 100 MHz and my co-worker in Japan tested 92 MHz as well. No problems for all the frequencies as long as you play <= 192 kHz. Only if you play 352.8kHz audio files on OSF mode, it's better to use 96 or 100 MHz.can I employ 90.3168 MHz master clock with Sabre dac?
( 90.3168 MHz = 4 x 22.5794 MHz = 4 x 512 x 44.1 KHz )
(To say exactly, 512 x 44.1 kHz = 22.5792 MHz )
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Thank you Bunpei,
I have the board bunpei mentions, the ElectrArt USB-Dual-Audio, and am now enjoying DSD playback from my PC to the ES9018 Buffalo-II DAC. Both 64fs 2.8Mhz and 128fs 5.6Mhz are supported, both playback and record. I started a thread with more details. Just want the DIY community to know DSD is here.
btw, price was $384 shipped to the US built and tested, including unpopulated DSD1794a DAC and PCM4202 ADC and meter/sample rate led pcb.
I have the board bunpei mentions, the ElectrArt USB-Dual-Audio, and am now enjoying DSD playback from my PC to the ES9018 Buffalo-II DAC. Both 64fs 2.8Mhz and 128fs 5.6Mhz are supported, both playback and record. I started a thread with more details. Just want the DIY community to know DSD is here.
btw, price was $384 shipped to the US built and tested, including unpopulated DSD1794a DAC and PCM4202 ADC and meter/sample rate led pcb.
Last edited:
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