This it is seems very promising. At least you can English, so it may be easier for some to get the right informations...
But how can you be so sure about AVCC as reference level for the whole ES9018 system? There is no any documentation to support a so statement. Much about this chip are speculations, hypothesis, or so, quite confuse informations. Very little is precise (datasheet).
AVCC it may have a connection with, or it may power an internal reference system or part of it, but I may not go so far to defined this power rail as the real reference for everything into the chip... Well another hypothesis...
Well, at least that guy refer to some of his measurements in the field of jitter, DAC immunity to this, and so. I just repeated his assertions. At least he measured and simulated jitter to observe the DAC behaviours...
The hypothetical schematic of the chip outputs it make quite much sense, as your thinking about AVCC more as a current source.
But there is a fact that variations in AVCC tension level (with also strong current capabilities) it have impact (+/-) for the outputted sound quality...
As I can only see so far are only the informations coming from measurements, which can be/remain solid in this case...
"However, to achieve a reference
that is sufficiently low noise, to not compromise overall
performance, requires an external voltage reference (AVcc).
Therefore, the node labeled AVcc (the analog power supply)
might better be called “DACReference” since it is the DAC
reference level."
http://www.esstech.com/PDF/sabrewp.pdf
that is sufficiently low noise, to not compromise overall
performance, requires an external voltage reference (AVcc).
Therefore, the node labeled AVcc (the analog power supply)
might better be called “DACReference” since it is the DAC
reference level."
http://www.esstech.com/PDF/sabrewp.pdf
He tears down AP2522!
https://www.youtube.com/watch?v=dWxI1G5Kumc
edit-
He has linear audio so he must know diyaudio.com.
https://www.youtube.com/watch?v=U6gNgD0Whh0#t=17m
https://www.youtube.com/watch?v=dWxI1G5Kumc
edit-
He has linear audio so he must know diyaudio.com.
https://www.youtube.com/watch?v=U6gNgD0Whh0#t=17m
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Based on my own policy, I do not trust those who use the term "jitter" without any further specification in the field of audio devices. A jitter which is subject to sound quality that audiophiles in this forum argue never be such property of electrical signal that you can simulate.
Instead, I do trust those who use and measure a "phase noise".
Dustin told about it.
The output stage is 64 or 65 switches connecting the output to AVCC or AGND through resistors, all of them in parallel. The analog output value is proportional to AVCC (therefore any noise on AVCC multiplies the differential output besides adding to the common mode voltage). It's validated by measurements.
The number of the MOS switches is 64 per one phase of one channel. That represents 65 levels of delta-sigma modulated values in a "thermometer coding" format with DEM. This configuration is called as "6 bit quantization". The equivalent internal resister value, 781.25 ohm, in their datasheet can be simply calculated by 50k ohm/64.
Any idea about details on how it may works RESET (global) for ES9018?
It may be active on zero. Any confirmation?
May be a hardware reset on the chip pin be readable on I2C lines, so to permit to the rest of a eventual system this DAC may be part of, to understand the need to reprogram (firmware) the chip registry?
It may be active on zero. Any confirmation?
May be a hardware reset on the chip pin be readable on I2C lines, so to permit to the rest of a eventual system this DAC may be part of, to understand the need to reprogram (firmware) the chip registry?
You can confirm your idea by looking at the circuit connected to the RESET pin shown on a schematic of ES9008 evaluation board.
http://www.esstech.com/PDF/Sabre_8_2Channel_64PIN_V3_SCH.pdf
I assume you had checked a datasheet before you posted this question.
As you may know, there is no documented register that holds any reset history.
The signal, RESET, is an one-shot pulse which is essentially required at a boot phase. Even if the pin is kept low for a long period, you can't read out this state. The chip is down at the period.
No programmer of firmware that controls the DAC chip in his commercial product assumes someone like you might make the RESET pin low.
Hi Bunpei
Thank you very much for the time you took to answer my questions. Appreciated your help.
When the chip is down while reset is active, then a firmware programmer should want to check its status (up or down). So such state should for sure be useful for the system/firmware...It may not be so reasonable to run a routine to setup the chip registry (through I2C lines), while the chip is down...
But is very right that such routine it may not be activated only by keeping down the reset pin...
Thank you very much for the time you took to answer my questions. Appreciated your help.
When the chip is down while reset is active, then a firmware programmer should want to check its status (up or down). So such state should for sure be useful for the system/firmware...It may not be so reasonable to run a routine to setup the chip registry (through I2C lines), while the chip is down...
But is very right that such routine it may not be activated only by keeping down the reset pin...
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Does anybody have any proven info on 5v-tolerant inputs of the Sabre? I'm finishing my own arduino code, Mega2560 here, and am now seriously concerned about i2c level conversion. Just found out that chinese ES9018 kits from ebay use low-voltage fed atmega chips, I was kinda sure before that they're 5v, and Sabre can safely eat 5v on i2c inputs; now I am not. Don't want to fry this lovely chip.
Thank you. I saw no reference to i2c pins as 5v-tolerant in the datasheet, thus asked. Theoretically, any i2c device must be 5v-tolerant, as it's an open drain bus and must be diode-clamped to Vcc. But isn't it safer to ask first?
Btw, a side effect. If a duino pulls i2c lines to 5V, there is some CONSTANT current flowing along these lines, from a pullup resistor through clamps to 3.3V source. This might add some unwanted noise, for arduinos use simple and cheapo power source (and are quite noisy themselves), instead of well-filtered Sabre PSU. Worth some thinking, imho.