Above about upgrading ES9038q2m on the example of SOUNDKEY PCM5102. I probably did not quite understand what was going on - then I apologize. But the same PCM5102 in this forum XMOS 384K/32bit PCM5102 DAC Мини - реальность., tried to bring to mind. And there it was clear that it should be untied from USB power. The same output filter is recommended to alter. Although initially on the dac everything corresponded to the datasheet. I myself personally have this DAC. And I can say that a separate power supply is better than powering the USB port. Therefore, simplification will not lead to improvements. I repeat - I may be due to the use of Google translator, I didn’t quite understand the essence of fashion or improvements.
The noise measurements are interesting to me. I will wait.
P.S. Does it make sense on this ES9038q2m to untie the USB amanero from the power of the USB port? And is it even possible?
The noise measurements are interesting to me. I will wait.
P.S. Does it make sense on this ES9038q2m to untie the USB amanero from the power of the USB port? And is it even possible?
@888777
you may find some useful info on the questions above from those links:
Модуль питания для ЦАП-а AH-PW6-mini
Гальваническая развязка для USB модуля Amanero.
regarding the regulators (not power supply), I believe they should be as close to the load as possible, e.g. 1 cm max. for the AVCC any decent low noise 3.3V reg + an op amp buffer should be OK. in order to improve of ESS typical lack of lows and exaggerated highs you may take a look at pretty low impedance regs at: Audio Perfection Forum - Источники питания . or put a lot of those film caps Mark recommends.
galvanic isolation of USB transport brings an improvement indeed, but then reclocking/sync mode might be required. instead of amanero one can take a look at I2SoverUSB - I2S over USB Audio. will be easier IMHO.
and of course, if you upgrade the oscillator, then again it deserves a dedicated reg (perhaps even dedicated PS). with some inductance in the path ir order to keep things clean. for the digital part the one on the board could be left, may be more capacitance added on the DACs legs. if I remember correctly, this was discussed at some point earlier.
you may find some useful info on the questions above from those links:
Модуль питания для ЦАП-а AH-PW6-mini
Гальваническая развязка для USB модуля Amanero.
regarding the regulators (not power supply), I believe they should be as close to the load as possible, e.g. 1 cm max. for the AVCC any decent low noise 3.3V reg + an op amp buffer should be OK. in order to improve of ESS typical lack of lows and exaggerated highs you may take a look at pretty low impedance regs at: Audio Perfection Forum - Источники питания . or put a lot of those film caps Mark recommends.
galvanic isolation of USB transport brings an improvement indeed, but then reclocking/sync mode might be required. instead of amanero one can take a look at I2SoverUSB - I2S over USB Audio. will be easier IMHO.
and of course, if you upgrade the oscillator, then again it deserves a dedicated reg (perhaps even dedicated PS). with some inductance in the path ir order to keep things clean. for the digital part the one on the board could be left, may be more capacitance added on the DACs legs. if I remember correctly, this was discussed at some point earlier.
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888777, it is not an upgrading project, I design dongle-like USB DAC+HPA for 4-wires headphones(only balanced output) from the scratch. As usual, a tiny sized device is full of compromises, in case of soundkey(which is just an example) it is too much compromised to me. My target is a tiny dongle with outstanding performances for that class devices: -120dbA S/N and THD+N .0005% at 1/2 max power or better. If I going to use simplified LPF, I can omit 2 opamp gates, and for 20x40mm PCB it's a big deal. Otherwise, I have to use these two opamp gates and surrounding parts, so my PCB could be 20x55mm, that's not so sexy as 20x40mm right? This is why I've interest regarding SE9038Q2M's out of band noise performance. Currently on my bench ak4490(simple 1st order LPF) USB DAC+HPA with 1.3MHz boost converter (4-5V in/5.5V out) and 5x1000uF Low-ESR solid-polymer caps + lots of X7Rs + beads, and I got S/N near to -121dbA, THD .0005%@-3db, however it is really bigger than typical USB flash dongle, and same sized as my PowerDAC YouTube
It's difficult to say what the quality of the regulators are without a schematic; N°3 has, and its based on a Walt Jung reg. I noticed the Vref had been replaced with a green LED, it may be low noise but the output will drift with temp, probably not important for most applications, but not good for AVCC.
You can buy a genuine Jung/Didden PCB from the store - link at the top of the page; yes, it probably is the more expensive option but your supporting your favourite web site
Hi Guys,
Back to explain something to anyone who may be interested, I was able to observe on the scope why a particular delay setting of the clock divider 150ps-step delay capability probably resulted in best sound quality. It turns out that the maximum delay setting available combined with other propagation delays in the clock dividing circuitry resulted in the 12.5MHz DSD data clock being exactly in phase as a subharmonic of the 100MHz dac chip MCLK. In other words, the two signals were aligned as perfectly together as could be, at least as viewed on a 100MHz scope.
What does it mean going forward? For one thing, it suggests D-flip flops may not be the ideal approach. Rather, it probably would make more sense to feed the Crystek (or similar) clock into the divider chip, and then use outputs of it to drive both the dac chip and the AK4137 (maybe with a little tweaking to align AK4137 DSD output with its clock input if there is any skew there). The reason is because the divider chip can synchronize the edges of all its output signals at a point in time chosen by the user. From then on the outputs will stay in relative sync until the next reboot. Or, as a likely even better approach, use a low frequency low-jitter SC cut ultra-low jitter clocks to feed an ultra-low jitter clock multiplier chip to produce the necessary clock signals. That way would likely result in the least jitter.
Hopefully, it is getting apparent this is getting quite a bit beyond the scope of modding low cost Chinese ES9038Q2M boards.
In addition, the test dac I have working now is good enough that with the right filter I think it could potentially stand a chance of equaling or even exceeding by a little bit the sound quality of DAC-3. They sound virtually indistinguishable to me now aside from what seems like could only, or very largely, be accounted for by the interpolation filter design. Only one way to find out though.
Thus, I think I will stop further experiments with modding my 2nd ever dac project (the 1st one being the earlier one described in this thread), and turn attention to doing some thinking about FPGA filters, including other use of other (hopefully) low cost chips besides Spartan 6.
Regarding prospects of embarking on a 3rd dac building journey, I think the forthcoming AK4499 looks very interesting, at least from what I know so far. Most likely a lot of what I have learned from this project would start off a new project at a more advanced point too. Could be tempting.
-Mark
Back to explain something to anyone who may be interested, I was able to observe on the scope why a particular delay setting of the clock divider 150ps-step delay capability probably resulted in best sound quality. It turns out that the maximum delay setting available combined with other propagation delays in the clock dividing circuitry resulted in the 12.5MHz DSD data clock being exactly in phase as a subharmonic of the 100MHz dac chip MCLK. In other words, the two signals were aligned as perfectly together as could be, at least as viewed on a 100MHz scope.
What does it mean going forward? For one thing, it suggests D-flip flops may not be the ideal approach. Rather, it probably would make more sense to feed the Crystek (or similar) clock into the divider chip, and then use outputs of it to drive both the dac chip and the AK4137 (maybe with a little tweaking to align AK4137 DSD output with its clock input if there is any skew there). The reason is because the divider chip can synchronize the edges of all its output signals at a point in time chosen by the user. From then on the outputs will stay in relative sync until the next reboot. Or, as a likely even better approach, use a low frequency low-jitter SC cut ultra-low jitter clocks to feed an ultra-low jitter clock multiplier chip to produce the necessary clock signals. That way would likely result in the least jitter.
Hopefully, it is getting apparent this is getting quite a bit beyond the scope of modding low cost Chinese ES9038Q2M boards.
In addition, the test dac I have working now is good enough that with the right filter I think it could potentially stand a chance of equaling or even exceeding by a little bit the sound quality of DAC-3. They sound virtually indistinguishable to me now aside from what seems like could only, or very largely, be accounted for by the interpolation filter design. Only one way to find out though.
Thus, I think I will stop further experiments with modding my 2nd ever dac project (the 1st one being the earlier one described in this thread), and turn attention to doing some thinking about FPGA filters, including other use of other (hopefully) low cost chips besides Spartan 6.
Regarding prospects of embarking on a 3rd dac building journey, I think the forthcoming AK4499 looks very interesting, at least from what I know so far. Most likely a lot of what I have learned from this project would start off a new project at a more advanced point too. Could be tempting.
-Mark
Markw4, any ideas why ES9038Q2M clock is always 100MHz(at least I saw so), and always as the oscillator(Xtall+logic gates inside)? I see 2 reasons to suspect the's not optimal:
a) I not always sure regarding the jitter of some 3.3V general purpose Osc-ICs but I pretty sure that ES9038Q2M can drive passive Xtall quite good, just because it is top level DAC.
b) 100MHz mentioned in the datasheet of ES9038Q2M as a maximal allowable.
a) I not always sure regarding the jitter of some 3.3V general purpose Osc-ICs but I pretty sure that ES9038Q2M can drive passive Xtall quite good, just because it is top level DAC.
b) 100MHz mentioned in the datasheet of ES9038Q2M as a maximal allowable.
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Hi Mark
Big congrats to you, you brought your project to an oustanding sonic level, and that is only your second DAC!!!
Yes, that last play around filters seems interesting to investigate and YES, all you learned can only be beneficial to what I see as another challenging, and for me very tempting project around the latest AKM chip!
Well done again
Claude
Big congrats to you, you brought your project to an oustanding sonic level, and that is only your second DAC!!!
Yes, that last play around filters seems interesting to investigate and YES, all you learned can only be beneficial to what I see as another challenging, and for me very tempting project around the latest AKM chip!
Well done again
Claude
Most likely because 100MHz is a standard clock frequency, and it is high enough to allow use of the dac, including the internal jitter reduction ASRC, with the highest digital audio sample rates.
From the standpoint of jitter, I would agree lower clock frequencies tend to be better.
The whole subject can get much more complicated, of course. But, I have given the you my quick answer.
Thanks, Claude! When people take interest in work I am doing it sure helps motivate me to keep trying to move forward.
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IVX, I don't think the choice of 100MHz is strange, I think it is because it is attractive to end users to be able to see how very high sample rate audio can sound. The reason for going to such high sample rates is because many people believe it is necessary for best sound quality, and dac buyers want the best sound quality within their budgets.
In other words, 100MHz helps to sell more dacs because dac buyers think it is what they want.
In regard to the other issue 'a' you ask about, the reason for using clock modules rather than simple crystals is because clock module are cheap enough, and the better ones can offer very low jitter, lower than the simple oscillator inside the dac chip can. I think the internal oscillator is for use in very low cost cell phone designs where small size and very controlled costs are paramount. It may be helpful to keep in mind that the dac chips are designed to have a set of features that can help sell high volumes of dac chips for different applications that sell at many different price points.
I think if you are curious to use a crystal then you should go ahead and try it. You would of course need to access the dac control registers over I2C bus to configure the clock oscillator drive level for the crystal you use.
In other words, 100MHz helps to sell more dacs because dac buyers think it is what they want.
In regard to the other issue 'a' you ask about, the reason for using clock modules rather than simple crystals is because clock module are cheap enough, and the better ones can offer very low jitter, lower than the simple oscillator inside the dac chip can. I think the internal oscillator is for use in very low cost cell phone designs where small size and very controlled costs are paramount. It may be helpful to keep in mind that the dac chips are designed to have a set of features that can help sell high volumes of dac chips for different applications that sell at many different price points.
I think if you are curious to use a crystal then you should go ahead and try it. You would of course need to access the dac control registers over I2C bus to configure the clock oscillator drive level for the crystal you use.
Hopefully, it is getting apparent this is getting quite a bit beyond the scope of modding low cost Chinese ES9038Q2M boards.
In addition, the test dac I have working now is good enough that with the right filter I think it could potentially stand a chance of equaling or even exceeding by a little bit the sound quality of DAC-3. They sound virtually indistinguishable to me now aside from what seems like could only, or very largely, be accounted for by the interpolation filter design. Only one way to find out though.
I think I told you a long time ago to set sights on surpassing DAC3.
I was pretty confident you would do it. I'm almost certain BM don't do critical
listening every step of the way as you have.
The 4499 interests me also. *Potentially better DAC. No ASRC to deal with.
Very tricky WRT I-V.
A worthy project.
T
NZ2520SD looks interesting but I can't find one for 80MHz on taobao yet, 49, 50 and 60MHz are quite cheap $.3 or about. Looks fishy to my.. I think a fake osc is possible due to the original NZ2520SD looks exactly like any noname 2520 sized osc and needs only laser-mark it according to NZ2520SD. On the other hand, it is difficult to test jitter/phase noise, for instance, I have no equipment for that, so I need to drive an hour to get some Rode & Schwartz for 30min and $50 for a lab rent.
Did you try Xtal at pins 28-29? What equipment you using to measure jitter? I personally believe SE9038Q2M was designed by a smart guy, and such pro for sure have idea how to build low noise Xtal oscillator into their DAC. Next, I googled a bit regarding jitter/phase noise contributors and found this Low Phase Noise Precision Crystal Solutions | Vectron International
As we can see, a standard 50MHz Xtal with reference quality osc has the same @1kHz phase noise as NZ2520SD 60MHz(-141db vs -142db). It means the oscillator circuity implementation is the dominant factor for phase noise figures, at least in the audio band. If the oscillator circuit in the ES9038Q2M designed with proper attention to details, and we have seen there dedicated power rail VCCA pin#27 that's a good sign, hence, we have a chance to get very high performance regarding jitter/phase noise even with ordinary Xtal at pins 28-29.
Did you try Xtal at pins 28-29? What equipment you using to measure jitter? I personally believe SE9038Q2M was designed by a smart guy, and such pro for sure have idea how to build low noise Xtal oscillator into their DAC. Next, I googled a bit regarding jitter/phase noise contributors and found this Low Phase Noise Precision Crystal Solutions | Vectron International
As we can see, a standard 50MHz Xtal with reference quality osc has the same @1kHz phase noise as NZ2520SD 60MHz(-141db vs -142db). It means the oscillator circuity implementation is the dominant factor for phase noise figures, at least in the audio band. If the oscillator circuit in the ES9038Q2M designed with proper attention to details, and we have seen there dedicated power rail VCCA pin#27 that's a good sign, hence, we have a chance to get very high performance regarding jitter/phase noise even with ordinary Xtal at pins 28-29.
@IVX,
Don't know what eziitis may say, but many people use the J-test feature in Arta to get an idea of jitter for a dac. Regarding clocks in particular, sound quality depends on how much jitter there is near the clock frequency. Usually, we are interested in how much jitter at 1Hz from the clock frequency and 10Hz from the clock frequency (called offset frequencies). Clocks appropriate for high quality audio should show in the data sheet how much phase noise there is at various offsets, either in a table format or as a graph. However, there are a few well known clocks that perform very well for audio even the manufacturer doesn't specify or guarantee their performance at low offset frequencies. NZ2520SD is a very good one of that type. In addition, you may notice that phase noise as a function of offset makes a graph that looks similar to 1/f noise. That is, the graph tends rise steeply at lower offset frequencies. That's why just measuring at 1kHz or even 100Hz offset is not enough information to evaluate clock quality for audio.
Don't know what eziitis may say, but many people use the J-test feature in Arta to get an idea of jitter for a dac. Regarding clocks in particular, sound quality depends on how much jitter there is near the clock frequency. Usually, we are interested in how much jitter at 1Hz from the clock frequency and 10Hz from the clock frequency (called offset frequencies). Clocks appropriate for high quality audio should show in the data sheet how much phase noise there is at various offsets, either in a table format or as a graph. However, there are a few well known clocks that perform very well for audio even the manufacturer doesn't specify or guarantee their performance at low offset frequencies. NZ2520SD is a very good one of that type. In addition, you may notice that phase noise as a function of offset makes a graph that looks similar to 1/f noise. That is, the graph tends rise steeply at lower offset frequencies. That's why just measuring at 1kHz or even 100Hz offset is not enough information to evaluate clock quality for audio.
IIRC, Arta's digital signal generator can produce a J-test signal. The resulting dac analog output can then be digitized and examined for spurs using Arta's spectrum analyzer. However, its possible I'm not remembering correctly. Regarding the manual, Arta's documentation can sometimes be lacking, IME.