ES9018K2M, ES9028Q2M, 9038Q2M DSD/I2S DAC HATs for Raspberry Pi

Hello everyone,

I've got a problem with the locks on the ES9038Q2M dac when using the ESS Controller in isolated mode and playing dsd128 material.
Setup:
  • Raspberry Pi 3B running DietPi v6.22.3 and Roon Bridge. Selected soundcard: i-sabre-k2m (so I can do dsd128) with PSU noise reduction 'on'.
  • FifoPi with the ESS Controller.
  • ES9038Q2M in sync mode and mclk connected to the FifoPi and setup described in part H of the ES9038Q2MPiDualMonoManualRev1 manual.
  • Standard OPA I/V output board.

The problem with this setup is that when playing dsd128 material I sometimes lose the lock on the right channel (the led goes off and than on again) and this is audible. When playing DSD64 or FLAC files the locks stay on and there are no problems.

With the ESS Controller attached to the DAC hat (non-isolated mode) dsd128 files play fine, the locks are on on the dac and no hickups.

Is someone willing to do the same setup as mine and let me know what the results are? Do the locks always stay on when playing dsd128 files?

With regards, Big Bird

PS: I did above setup with 2 FifoPi's. The first one lost both locks and the second on only the right channel. I also tried Moode with the same soundcard settings and piCorePlayer with the Generic/simple ess9023 dac as soundcard. In both setups when playing dsd128 they lose the right lock.
 
What do you use to power the rpi? The latest ones are very power hungry and can consume over 2 amps under load and when the power supply is at its limit it gets very noisy. Maybe the DoP and the controller are enough to push it to the limit.
Is use the 5V rail from the LifePO4 power supply but I will try a switch mode power supply that is rated at 5V, 2A and will let you know if it solves my problem.
 
This is the information I see when the dac loses right lock.
 

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1. No difference when the ESS controller is directly plugged in.

2. With DoP function disabled the ES9038Q2M does not lose locks.

1. Please run it in both async mode (without MCLK feed from FifoPi and jumper to async) and sync mode (with MCLK from FifoPi and jumper to sync mode) to see what's the difference.

2. On ESS controller, what your DPLL bandwidth of DSD ?

Ian
 
1. Please run it in both async mode (without MCLK feed from FifoPi and jumper to async) and sync mode (with MCLK from FifoPi and jumper to sync mode) to see what's the difference.

2. On ESS controller, what your DPLL bandwidth of DSD ?

Ian
1. In async mode the right channel does not lose its lock when playing a dsd128 file. DPLL bandwidth 10. In async mode right channel loses lock when playing a dsd128 file.

2. In sync mode I use DPLL bandwidth 1.
 
I just tried DPLL bandwitch 2 in sync mode and then the right channel does not lose its lock with dsd128 file.

It seems the issue is fixed, so for now you can either have DPLL bandwidth set at 2, or going with internal DoP decoder (DAC will use PCM DPLL in this case)

ESS9038Q2M DSD DPLL design is not as good as PCM DPLL, you can try better XOs for FifoPi to see if it can work with DSD DPLL 1.

Regards,
Ian
 
It seems the issue is fixed, so for now you can either have DPLL bandwidth set at 2, or going with internal DoP decoder (DAC will use PCM DPLL in this case)

ESS9038Q2M DSD DPLL design is not as good as PCM DPLL, you can try better XOs for FifoPi to see if it can work with DSD DPLL 1.

Regards,
Ian
I only got three remaining quesstions:

  1. I already got two crystek CCHD957 clock oscillators installed so these are not good enough for DSD DPLL 1?
  2. Then why is it that when I have the ESSController is running in none-isolated mode i.e. attacched to the ESS9038Q2M that DSD DPLL 1 runs fine without losing locks? Both with the default clocks and the crystek clocks?
  3. Why does the ESS9038Q2M lose both locks when connected to another FifoPi and only lose the right lock with the current FifoPi?

With regards, Big Bird.
 
I only got three remaining questions:

For the dac to operate stably with DPLL=1 requires low incoming jitter. All sorts of things can affect jitter, including loose connections where the clocks plug into the clock sockets, bad or noisy connections is pin headers between the stacks of RPi and dac boards, etc. Jitter might not be fully attenuated by the isolator chips typically used for isolation of I2S and I2C signals. Power supply noise/connections can also affect jitter. Since RPi are known to be jittery there could be contributions from more than one source, and a noisy RPi could push the system into failure. Switching power supplies for RPi could have an effect. If using battery power supplies, wires between the dac and the batteries could have bad connections or be too long. A relay with noisy contacts on the battery board could cause problems.

Regarding the location of the controller. When on the dirty side the controller runs on dirty power. It talks to the dac over I2C bus through isolator chip(s). When on the clean side, it runs on clean power and I2C signals do not pass through isolators.

Because there are so many possibly factors that could cause DPLL instability at very low bandwidth settings, it may be hard for Ian to give you an definitive answer to each of your questions.

It might be helpful if you could post high res pictures of your dac and RPi that shows all the boards, power supplies, and interconnection wiring as clearly as possible, maybe that would give people not there with you some ideas about what to try that might help.