Electronic Design 201 type question... I know too little about straight digital technology and design, how would one implement a straight delay in the digital domain somewhere in the CD data stream???
A degree of setability or variability of delay would be peachy keen.
Standalone, PC operated, or data downloaded from a PC, ok. BUT, butte simple is best.
Options:
- SPDIF delayed
- Data after the DF delayed
Why I don't want to simply use a commercial "digital delay"?
Reason: ca-ca sound, ca-ca components, ca-ca opamps, and another layer of A/D - D/A.
Anyone who can suggest the general technique, and especially text books, articles or online resources to help, and/or applications to see as examples would be greatly appreciated!!
I need to be able to understand it well enough to attempt an implementation - without having to take several semesters of EE courses. 😀
Fwiw, 64meg PC memory sticks are ubiquitous and virtually free these days - building block?
Regards,
_-_- digitally ignorant bear
A degree of setability or variability of delay would be peachy keen.
Standalone, PC operated, or data downloaded from a PC, ok. BUT, butte simple is best.
Options:
- SPDIF delayed
- Data after the DF delayed
Why I don't want to simply use a commercial "digital delay"?
Reason: ca-ca sound, ca-ca components, ca-ca opamps, and another layer of A/D - D/A.
Anyone who can suggest the general technique, and especially text books, articles or online resources to help, and/or applications to see as examples would be greatly appreciated!!
I need to be able to understand it well enough to attempt an implementation - without having to take several semesters of EE courses. 😀
Fwiw, 64meg PC memory sticks are ubiquitous and virtually free these days - building block?
Regards,
_-_- digitally ignorant bear
64 MB? How much of a delay are you looking for? You could literally get several minutes of delay in 64 MB. That's overkill, don't you think? Also, DRAM requires a lot of effort to use, because it needs to be refreshed. SRAM is much better. You can salvage 32 kB to 128 kB SRAM chips from DIP sockets in older 486 through Pentium motherboards (the L2 cache). 128 kB gives you enough space for just under 1 second of delay at 44.1 kHz, 16 bit, 2 channel.
So how would you make use of this RAM? Well, first I would try to delay the I2S audio signals (like what is inside the CD player or DAC) rather than S/PDIF, because clock signals are available with I2S. When I say I2S, I really mean any of a number of slightly different formats including left-justified, right-justified, and "proper" I2S. The I2S audio is sent serially, with one bit per bit clock. Then there is a L/R or Word clock (WCLK), which transitions to High for Left and to Low for Right (although sometimes the other way around). If you don't know the format used, then you don't know which 16 (or more) of the 32 bits per sample need to be stored, so you could just store them all. So what you want is some way to capture the 64 bits (2 channels)sent every I2S WCLK period, store these as 8 bytes, lookup a previously stored 8 bytes, and transmit those serially. You could break this down and do it in 32 bit increments, on both transitions of the WCLK (hi and low), or just do it every 8 bits, although you need to maintain synchronisation to the WCLK.
One way to avoid the dirty work is to use a serial FIFO chip. These are not cheap and may be tricky to keep synchronised, so you just create other dirty work. Another way is to use one or more serial-to-parallel shift registers, then store the resulting parallel data in the RAM, and load older parallel data from the RAM into one or more parallel-to-serial shift registers. You could use the WCLK to latch data into/out of the shift registers. You need to make sure to sample the incoming data on the rising edge of the bitclock, and transmit data on the falling edge. This would probably require a microcontroller or some other smarts to generate the read and write addresses for the SRAM and to coordinate the reading and writing.
You might be able to tell that I have given this some thought in the recent past. I haven't built anything yet though. Anyway the above should answer a couple questions and make you ask yourself a whole lot more of them.
So how would you make use of this RAM? Well, first I would try to delay the I2S audio signals (like what is inside the CD player or DAC) rather than S/PDIF, because clock signals are available with I2S. When I say I2S, I really mean any of a number of slightly different formats including left-justified, right-justified, and "proper" I2S. The I2S audio is sent serially, with one bit per bit clock. Then there is a L/R or Word clock (WCLK), which transitions to High for Left and to Low for Right (although sometimes the other way around). If you don't know the format used, then you don't know which 16 (or more) of the 32 bits per sample need to be stored, so you could just store them all. So what you want is some way to capture the 64 bits (2 channels)sent every I2S WCLK period, store these as 8 bytes, lookup a previously stored 8 bytes, and transmit those serially. You could break this down and do it in 32 bit increments, on both transitions of the WCLK (hi and low), or just do it every 8 bits, although you need to maintain synchronisation to the WCLK.
One way to avoid the dirty work is to use a serial FIFO chip. These are not cheap and may be tricky to keep synchronised, so you just create other dirty work. Another way is to use one or more serial-to-parallel shift registers, then store the resulting parallel data in the RAM, and load older parallel data from the RAM into one or more parallel-to-serial shift registers. You could use the WCLK to latch data into/out of the shift registers. You need to make sure to sample the incoming data on the rising edge of the bitclock, and transmit data on the falling edge. This would probably require a microcontroller or some other smarts to generate the read and write addresses for the SRAM and to coordinate the reading and writing.
You might be able to tell that I have given this some thought in the recent past. I haven't built anything yet though. Anyway the above should answer a couple questions and make you ask yourself a whole lot more of them.
New Lip-Sync Delay ICs
Texas Instruments has some new audio delay ICs that might do just what you're looking for. They're presently in prerelease.
They do a direct delay on a digital I2S data stream, adjustable from 0 to 170mS (at fs = 48kHz). Multiple devices can be put in series for more delay.
Depending on your application, they could be inserted just about anywhere you have an I2S data stream. To patch it into an existing circuit, it would only be necessary to cut the I2S data line. The part also would require attachment to BCLK and LRCLK (no cuts necessary). The part operates on +3.3V.
The part is a 16pin QFN surface mount package with a thermal pad. If you don't want to make a PC board for it, it can be glued upside down on its back and a small u-shaped piece of copper can be soldered to the pad (heat the copper before bringing it into contact with the part). 30AWG wire wrap wire is fairly straightforward to solder to the terminals. (It might be practical to glue it on top of an existing IC, lining up the power pins.)
The TPA5050 is a version with I2C control:
http://focus.ti.com/docs/prod/folders/print/tpa5050.html
It would either require a small microcontroller, or rigging something to control the I2C lines from a PC port. Delays can be adjusted in increments of one sample period.
The TPA5052 is a version with direct hardware pin control.
There's no data sheet available for this yet. It probably will be easier to use as a standalone part, but I'm guessing that the delay will have a coarser adjustment.
Regards,
Brian.
Texas Instruments has some new audio delay ICs that might do just what you're looking for. They're presently in prerelease.
They do a direct delay on a digital I2S data stream, adjustable from 0 to 170mS (at fs = 48kHz). Multiple devices can be put in series for more delay.
Depending on your application, they could be inserted just about anywhere you have an I2S data stream. To patch it into an existing circuit, it would only be necessary to cut the I2S data line. The part also would require attachment to BCLK and LRCLK (no cuts necessary). The part operates on +3.3V.
The part is a 16pin QFN surface mount package with a thermal pad. If you don't want to make a PC board for it, it can be glued upside down on its back and a small u-shaped piece of copper can be soldered to the pad (heat the copper before bringing it into contact with the part). 30AWG wire wrap wire is fairly straightforward to solder to the terminals. (It might be practical to glue it on top of an existing IC, lining up the power pins.)
The TPA5050 is a version with I2C control:
http://focus.ti.com/docs/prod/folders/print/tpa5050.html
It would either require a small microcontroller, or rigging something to control the I2C lines from a PC port. Delays can be adjusted in increments of one sample period.
The TPA5052 is a version with direct hardware pin control.
There's no data sheet available for this yet. It probably will be easier to use as a standalone part, but I'm guessing that the delay will have a coarser adjustment.
Regards,
Brian.
Cool.
There's another mfrs chip that I am also looking into that does the same trick.
Apparently they are intended for TVs that do heavy sound processing, creating or maybe it is video processing - yeah that makes sense - so the audio needs to be delayed to make lip sync.
This sounds like it has some real potential.
Thanks for the heads up!!
BTW, not sure what you are referring to with the "U" shaped something or other - what is that for, go between what and what??
_-_-bear
There's another mfrs chip that I am also looking into that does the same trick.
Apparently they are intended for TVs that do heavy sound processing, creating or maybe it is video processing - yeah that makes sense - so the audio needs to be delayed to make lip sync.
This sounds like it has some real potential.
Thanks for the heads up!!
BTW, not sure what you are referring to with the "U" shaped something or other - what is that for, go between what and what??
_-_-bear
bear said:
This is to act as a heatsink.
The TPA5050 is a surface mount part with a pad on the underside to couple the internal die to a plane on a PC board for thermal transfer.
One way to kludge / prototype with these parts is to mount them upside down and solder a small 'U' shaped piece of copper to the bottom pad to act as a heatsink.
Regards,
Brian.
Hey!
Beautiful work!
That dac + delay must have been a ton of man-hours?
Nice looking round horn too!
😀
_-_-bear
Beautiful work!
That dac + delay must have been a ton of man-hours?
Nice looking round horn too!
😀
_-_-bear
bear said:Hey!
Beautiful work!
That dac + delay must have been a ton of man-hours?
_-_-bear
Yes I spend a long time designing it, but it incorporatres many other functions. Everything exept power amp for a 3 way horn active system.
Hi,
After 4 more years I went much further in the multichannel DAC + delay + crossover + volume control!
All details here:
TOTALDAC board
Sorry this is now a commercial web site, I am starting a new company to sell this DAC.
After 4 more years I went much further in the multichannel DAC + delay + crossover + volume control!
All details here:
TOTALDAC board
Sorry this is now a commercial web site, I am starting a new company to sell this DAC.
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