Has 2 diamonds.
One for the input and one for the output.
Current Feedback goes back to the input part.
R20 must be 2 Watt.
THD 0.00018% (-114.9dB)
One for the input and one for the output.
Current Feedback goes back to the input part.
R20 must be 2 Watt.
THD 0.00018% (-114.9dB)
In open-drain, the output has additional voltage gain, which can then be added to the global loop. As a source follower, distortion from gate-drain capacitance appears to bypass the local feedback, so it relies on the global loop to help linearise it.
Is the approx 3:1 distortion advantage for the source-follower a good use of the Exicons' approx. 15x voltage gain @8 ohm?
The other (possibly bigger) benefit I see is that the voltage swing at the MOSFET gates is reduced to around ±0.5 ~ 1V, which helps the VAS retain linearity.
But it's an open question whether those benefits outweigh other possible issues.
Higher MOSFET distortion + possibly cleaner VAS,
Or: cleaner MOSFET + rail-to-rail VAS?
Is the approx 3:1 distortion advantage for the source-follower a good use of the Exicons' approx. 15x voltage gain @8 ohm?
The other (possibly bigger) benefit I see is that the voltage swing at the MOSFET gates is reduced to around ±0.5 ~ 1V, which helps the VAS retain linearity.
But it's an open question whether those benefits outweigh other possible issues.
Higher MOSFET distortion + possibly cleaner VAS,
Or: cleaner MOSFET + rail-to-rail VAS?
I do know, of course. Have you ever made a comparison? I did, and the results with common emitter (source) output stage with gain and output from collectors (drains) have always been worse, than with 2EF, feedback included.
I never build my designs.
I leave it to other guys here to try my ideas.
I tweaked this amplifier a lot. To acheive THD 0.00018%.
This amp will work. I have no doubt.
Like current feedback amps it is fast.
Like many other "famous" designers. The only problem is that you often overlook major circuit issues that are unclear in a mere simulation.
Yes! SImulators assume many things that are not true in real life. PCB layout is another thing that will keep many circuits from coming close to the performance target.
You have got to build some stuff. That's the only way you really know if it works, how well it works and what components the design is sensitive to. In other words, reality.
You have got to build some stuff. That's the only way you really know if it works, how well it works and what components the design is sensitive to. In other words, reality.
Like the saying, "in theory, theory and practice are the same, but in practice they're different." No argument there. But the suggestion was that something was wrong, just by looking at the circuit, but as usual the experts are coy about what that something is.
Hi Guys
I generally like Lineup's ideas 🙂
This amp is just a standard current-mode amp with the output bias control eliminated or preset. The second diamond has its passive current sources R15,16 which limit the slew rate into the mosfet gates. This might be improved with 2-transistor feedback-type current sources.
Output bias is tenuous, relying on the Vbe of the driver plus the voltage drop across R13,14. Where the mosfet current ends up will be a guess and require trial and error to get it to a safe place. Big companies set idle using a distortion analyser, as there will be a very narrow current value range where THD plummets but is high to either side. One might argue that going for a class-A bias level would reduce THD the most, but that is not always the case.
The active current sources could provide a means to accurately set the idle current. A current-sense resistor in the drain of the mosfet could be used for this function, as there are advantages to having the output tied to the output stage directly instead of through source/emitter resistors. There is the contrary argument that the source/emitter resistors help keep the output stage impedance from going negative at high frequencies. Better minds than mine likely know.
I generally like Lineup's ideas 🙂
This amp is just a standard current-mode amp with the output bias control eliminated or preset. The second diamond has its passive current sources R15,16 which limit the slew rate into the mosfet gates. This might be improved with 2-transistor feedback-type current sources.
Output bias is tenuous, relying on the Vbe of the driver plus the voltage drop across R13,14. Where the mosfet current ends up will be a guess and require trial and error to get it to a safe place. Big companies set idle using a distortion analyser, as there will be a very narrow current value range where THD plummets but is high to either side. One might argue that going for a class-A bias level would reduce THD the most, but that is not always the case.
The active current sources could provide a means to accurately set the idle current. A current-sense resistor in the drain of the mosfet could be used for this function, as there are advantages to having the output tied to the output stage directly instead of through source/emitter resistors. There is the contrary argument that the source/emitter resistors help keep the output stage impedance from going negative at high frequencies. Better minds than mine likely know.
I would suggest always put those resistors to the design. If they are not necessary, you can just put jumper and mark 0 Ohm on the board.
Same for miller cap location. Even it doesn't need, leave the mounting hole on the board without installing the component.
BTW, I don't think OP has enough phase margin. It relies on the internal capacitance of MJE243/MJE253 to do the compensation. What if I replace them with some fancy 200MHz fT ones. People often get caught by this off guard.
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Lineup has been encouraged by me and a number of other members to always do a loop gain/phase plot. It is the one of most important pieces of information any amplifier designer can provide.
It looks like we haven’t managed to convince him yet.
Given that this is a CFA design, C2 means it will absolutely be unstable. Never use a phase lead cap across Rf in a CFA!
🙁
It looks like we haven’t managed to convince him yet.
Given that this is a CFA design, C2 means it will absolutely be unstable. Never use a phase lead cap across Rf in a CFA!
🙁
Absolutely true.
But maybe some people are not interested in reality.
Just the screen in front of them.
Which is of course perfectly fine.
Everyone in the free world can do what he wants in private.
To put it out in public without explicit warning is something else.
What if someone actually takes the trouble and expenses to build and gets stuck.
Who is then there to sort things out for them ?
Cheers,
Patrick
Loopgain stability, DC currents stability with temperature, step response with complex load - all of those are necessary to investigate in simulation before one suggests the design in public. The best way is definitely to build a sample.