Hello,
This is my first thread and I have a problem with demultiplexing the digital PCM audio data stream.
Recently I designed a discrete R-2R DAC using information from the I2S spec sheet and wiki,
but when i first tested it, the output wave is split in 2: upper part and lower part.
I later found out that the PCM stream is coded as a signed integer using the 2's compliment method
but the shift-register can only decode a unsigned integer.
My question is if theres anyway I could change the signed PCM stream into unsigned?
OR
Is there another way of decoding this PCM Stream?
Thanks,
Boris
This is my first thread and I have a problem with demultiplexing the digital PCM audio data stream.
Recently I designed a discrete R-2R DAC using information from the I2S spec sheet and wiki,
but when i first tested it, the output wave is split in 2: upper part and lower part.
I later found out that the PCM stream is coded as a signed integer using the 2's compliment method
but the shift-register can only decode a unsigned integer.
My question is if theres anyway I could change the signed PCM stream into unsigned?
OR
Is there another way of decoding this PCM Stream?
Thanks,
Boris
Thanks for your Advice
But i have tried that and it seems that the mid-point is out of place
is there a way to fix it?
Another question: the output wave seems to have some of its voltage levels shifted vertically, is this caused by the resistor errors in the R-2R ladder?
I will try to get a photo from my oscilloscope ASAP.
Thanks,
Boris
But i have tried that and it seems that the mid-point is out of place
is there a way to fix it?
Another question: the output wave seems to have some of its voltage levels shifted vertically, is this caused by the resistor errors in the R-2R ladder?
I will try to get a photo from my oscilloscope ASAP.
Thanks,
Boris
Invert (and add one) will give the "inverse" voltage:
http://en.wikipedia.org/wiki/Two's_complement#Calculating_two.27s_complement
http://en.wikipedia.org/wiki/Two's_complement#Calculating_two.27s_complement
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With an adder? You can get a chip which will do this, and deal with carry in and out. Known as a 'full adder'.
What do you mean by "mid-point is out of place"? Digital zero of twos complement (2C) signal is 0000. Maximum positive value is 7FFF, maximum negative value is 8000. If you invert the MSB, these numbers will be 8000 (analog zero), FFFF (maximum positive signal), and 0000 (maximum negative signal), respectively. Exactly the 0000 to FFFF offset binary (OB) span.
By "Out of place" I meant the analogue signal, every time the wave crosses the analogue mid-point a positive spike appears.
That is called glitch, caused by imperfect switches. Do you have a sample-and-hold circuit after the DAC? That should hold the previous analog level during the glitch. I have built a similar R-2R discrete DAC, but I could reach 10-bit resolution with stock 0,1% resistors. The remaining 6 bits had to be trimmed.
WOW that is some amazing accuracy, i am only using ordinary 1% metal-film resistors
at with 24-bits, does the error tolerance really affect the output so much to cause glitches?
These "glitches" seems to be quite systematic so i was thinking they shouldn't be caused by the resistors' random error.
at with 24-bits, does the error tolerance really affect the output so much to cause glitches?
These "glitches" seems to be quite systematic so i was thinking they shouldn't be caused by the resistors' random error.
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The problem is that MSB changes from 0 to 1 around zero analog signal, so it has the most effect at zero crossing. MSB error should be less than the LSB value, i.e. 1/65536 that is 0.000015, in other words 0.0015%. You need at least this precision (and thermal coefficient) for true 16-bit. 0.1% is good for 10-bit. 1% is good for about 8-bit. Glitch error (which is independent from the above) makes this even worse.
I see, Thank you very much for the information.
guess I'll have to rebuild my DAC.
By the way, what value of R did you use for the R-2R Ladder?
guess I'll have to rebuild my DAC.
By the way, what value of R did you use for the R-2R Ladder?
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You mentioned a shift-register, so I assumed you used this to present the data in parallel form to your ladder network. In serial format I guess you just need a 1-bit adder, with a flip-flop to store carry bits.
I used 100k 0.1% Vishay resistors, 2R were two in series. The switching FETs are 0.2 ohm Rdson types. I still have the circuit digram somewhere. But I abandoned the project because it is nearly impossible to reach better than 10-11-bit accuracy. Search for "Linearity test CD" for my testing method.
Without actually analyzing the circuit, my first guess would be that stray and parasitic capacitance (such as D-G and D-S capacitance of the FET's) would be the main performance limitation at this impedance level. Is that incorrect?
Dale
I used a totem-pole topology, where the upper FET switched the resistor elements +12V and the lower FET switched it to GND in opposite phase. This way I tried to keep the source impedance close to zero. Then I connected the output to a noninverting opamp for minimum load. Stray capacitance across the resistors could be a limiting factor indeed.
0.1% error (of the MSB) means 0.001. That is 8 bit accuracy. That's where the problem starts. Linearity is at the same 8bit level.
Selecting the resistors might help - but only if you have a lab-grade DMM capable of better resolution and if you have a boatload of resistors.
Selecting the resistors might help - but only if you have a lab-grade DMM capable of better resolution and if you have a boatload of resistors.
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