Hi,
I was studying the bottom of the page 1 in the schematic (post #7 above). I guess it is all about selecting the L R channels - am I right? Boy, my brain hurts! I am wondering what is wrong with just using the WS for one channel and the inverted WS for the other one as 74hc595 is triggered by the rising edge of the WS signal. Is the worry about one channel getting late by one BCLK period in that case? If so, why can't one use a flip-flop with complementary outputs such as MC74AC74? According to data sheet there seems to be identical delays from clock to both inverted and non-inverted outputs. Are there any basic issues I am missing?
I was studying the bottom of the page 1 in the schematic (post #7 above). I guess it is all about selecting the L R channels - am I right? Boy, my brain hurts! I am wondering what is wrong with just using the WS for one channel and the inverted WS for the other one as 74hc595 is triggered by the rising edge of the WS signal. Is the worry about one channel getting late by one BCLK period in that case? If so, why can't one use a flip-flop with complementary outputs such as MC74AC74? According to data sheet there seems to be identical delays from clock to both inverted and non-inverted outputs. Are there any basic issues I am missing?
Hi murat,
You are right, this could be more simple, but it's not that simple. Both channels should be latched at the same time, otherwise there would be a phase difference between channels for a WS half-period, or 32 BCLK. 74HC595 for both channels are chained and lathed simultaneously. The latching edge should come from an inverted WS and be delayed for one inverted BCLK (SCK) cycle (negative edge triggered D flip-flip is not that common). I made a pulse, now I'am not sure why.
Thanks a lot for the kind answer. I am still trying to digest all of these and "I2S bus specification" from Philips, 1986 & 1996, in lights of the figures 5-7.
https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
For now (probably I will come back😉) may I ask you the following: You said "74HC595 for both channels are chained and lathed simultaneously." Does that mean that the "SDOUT" coming out of the last 595 on your second page goes into the other channel's 595 chain so that you are strobing them simultaneously? This may sound obvious but this is the fist time I am really noticing the issue.
https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
For now (probably I will come back😉) may I ask you the following: You said "74HC595 for both channels are chained and lathed simultaneously." Does that mean that the "SDOUT" coming out of the last 595 on your second page goes into the other channel's 595 chain so that you are strobing them simultaneously? This may sound obvious but this is the fist time I am really noticing the issue.
Actually in the past I used to think that WS period / 2 issue must have been introduced during ADC and then after DAC relative timing between the channels should have been restored. That was my poor thinking. Now you have opened a new horizon.
You're welcome! 🙂
This isn't in compliance with the following statements of the "I2S bus specification",
Yes, it can be seen on the first page, SDOUT is connected to next SDIN.
This isn't in compliance with the following statements of the "I2S bus specification",
but it's great circuit simplification as the I2S transmitter word length (actual sample data length can vary) is configured and known.
LOL.. I have looked at the first page for maybe about an hour and I would still be oblivious if you haven't mentioned.
BTW, I think I have started to notice something and would like to share. First, I am quite novice about the inner workings of shift registers and such. Still I will make an attempt to interpret the Figure 7 in that I2S bus specification sheet. First, I see MSB and LSB inside the register. This might (not necessarily) suggest that the data belongs to one channel only. But, more interesting is to see the LEFT and RIGHT boxes at top of the figure. I assume they are parallel outputs to be selected (Or??). They seemed to be enabled with the commands (WSP AND not WSD) for left and (WSP AND WSD) for right. So, it looks like they can not be enabled simultaneously but rather selected like left, right, left, right and so on. How do you think?
BTW, I think I have started to notice something and would like to share. First, I am quite novice about the inner workings of shift registers and such. Still I will make an attempt to interpret the Figure 7 in that I2S bus specification sheet. First, I see MSB and LSB inside the register. This might (not necessarily) suggest that the data belongs to one channel only. But, more interesting is to see the LEFT and RIGHT boxes at top of the figure. I assume they are parallel outputs to be selected (Or??). They seemed to be enabled with the commands (WSP AND not WSD) for left and (WSP AND WSD) for right. So, it looks like they can not be enabled simultaneously but rather selected like left, right, left, right and so on. How do you think?
I am still not insisting on the idea but if Mr. Nyquist was right about the reconstruction, then maybe it would be OK to sample left and right channels at different times. Though I also find this a pretty ugly idea...
Long time ago I also experimented with R-2R discrete DAC:
https://www.diyaudio.com/community/...-this-time-for-the-diyer.353709/#post-6186621
I soon realized that the resistor tolerances should be 0.1% or better, and even then some adjustment is needed. Not only the tolerance matters, but also the TK. A S/H type deglicher is also important. I used low Rds P-channel and N-channel Mosfets (0.25 ohms if I remember). This project has never been completed.
https://www.diyaudio.com/community/...-this-time-for-the-diyer.353709/#post-6186621
I soon realized that the resistor tolerances should be 0.1% or better, and even then some adjustment is needed. Not only the tolerance matters, but also the TK. A S/H type deglicher is also important. I used low Rds P-channel and N-channel Mosfets (0.25 ohms if I remember). This project has never been completed.
I think this circuit satisfies their requirement regarding unknown I2S transmitter word length and puts left and right sample data in different registers, but does not take into account the D/A start-of-conversion moment.
They (two signals) can be sampled simultaneously or interleaved, but D/A conversion must follow the same scheme. Otherwise, there would be a phase difference between reconstructed signals. What Mr. Nyquist say differently?
I have proof that this circuit works fine with latching/converting both channels simultaneously. 11.025 Hz signal with 44.100 Hz sample rate. No phase difference.
@lcsaszar
To be honest, I don't understand this schematic 🙂 Part with tubes, MOSFET, and logic gates 🙂 But looks like there is an error in the R-2R network. Shouldn't that be 2R, not R?
Yes, but this should be 2R (100k), not 100k || 100k.
R1 || R2 = R
(R1||R2) + R3 = 2R
((R1||R2)+R3) || R4 = R, and so on...
R1 || R2 = R
(R1||R2) + R3 = 2R
((R1||R2)+R3) || R4 = R, and so on...
Thanks, I will fix it. The whole design was based on the idea of trimming the upper bits. For the trimming a built-in generator was used that generated n+1, n and n-1 levels in sequence, that could be observed on an oscolloscope and trimmed so that the analog level of n falls between n+1 and n-1.
With trimming one doesn't need extreme tolerance resistors, 0.1% will do.
With trimming one doesn't need extreme tolerance resistors, 0.1% will do.
Perhaps you would be better served starting from the premise that it all works, free of any interchannel delay, and has done for more than 40 years.
Thanks much to both enaB and rfbrw. Actually enaB rephrased best what I really meant:
BTW, enaB, what is the source of the 11.025 Hz signal? A test track on a CD or a computer or...? What an impressively clean and repeatable data is that.
BTW, enaB, what is the source of the 11.025 Hz signal? A test track on a CD or a computer or...? What an impressively clean and repeatable data is that.
👍
@lcsaszar, Vref is short-circuited to GND in every bit transition by very low Rds(on) MOSFET-s.
A computer, signal generator in REW software. I have only a USB connection for this prototype DAC.
Could be. But there is another issue with this, and that is IRF7317 shoot-through.
@lcsaszar, Vref is short-circuited to GND in every bit transition by very low Rds(on) MOSFET-s.