Hi all,
I am thinking of building a hybrid passive-active RIAA preamplifier for MM cartridges. I want it to have JFETs at the input to reduce current noise and get rid of issues such as DC offset (which is more or less inevitable with BJTs because of base current flowing through the biasing resistor).
I am attaching the circuit diagram of a simple discrete opamp with cascoded JFET input which is driving a BJT LTP loaded with a current mirror. Do you think it would work?
I'd like to use it as a flat gain stage followed by a passive RC network for the 75us corner of the RIAA EQ curve. The second stage will supply additional 20dB of gain at 1kHz using active equalisation for the 318us and 3180us time constants.
I am thinking of building a hybrid passive-active RIAA preamplifier for MM cartridges. I want it to have JFETs at the input to reduce current noise and get rid of issues such as DC offset (which is more or less inevitable with BJTs because of base current flowing through the biasing resistor).
I am attaching the circuit diagram of a simple discrete opamp with cascoded JFET input which is driving a BJT LTP loaded with a current mirror. Do you think it would work?
I'd like to use it as a flat gain stage followed by a passive RC network for the 75us corner of the RIAA EQ curve. The second stage will supply additional 20dB of gain at 1kHz using active equalisation for the 318us and 3180us time constants.
Attachments
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Yes, the simulation does work, and I even took some care to calculate the operating points of the circuit (instead of my usual guesswork).
I actually started with a PNP LTP for the 2nd stage, but later flipped everything after the input stage around to take advantage of the same reference voltage for all three current sources.
I actually started with a PNP LTP for the 2nd stage, but later flipped everything after the input stage around to take advantage of the same reference voltage for all three current sources.
Attachments
If a circuit of this type works as a simulation OK then it should be transferable to a real build without to much drama. It might be worth trying different model JFET's to be sure its not on a knife edge somewhere but otherwise if it works... it works and should do for real.
I am very confident in the input stage because I lifted it almost verbatim from the LSK489 application notes written by Bob Cordell 😀 And much less confident in everything else because I did it myself, but then again a basic discrete opamp is no rocket science...
Played with different low noise JFETs in LTSpice -- they all seem to work well. Interestingly, 2SK246 simulates a touch better than the LSK489, but I'm going to stick with the LSK489 because of availability and low input capacitance. Maybe I will replace the cascode JFETs with 2SK117, I have several matched pairs that I bought a long time ago for an abandoned project, they should work in this position just as well.
There is only 1mA in Q2.
Leaving only 0.5mA in Q4 and Q1.
This seems to be on the lower side.
Leaving only 0.5mA in Q4 and Q1.
This seems to be on the lower side.
Thanks lineup, I started with a "self-biasing" cascode, and that configuration worked better when the current flowing in the 2nd stage was lower than the current flowing in the input stage. I later decided to use a potential divider to position the gates of cascode JFETs at 1/2 of the positive supply voltage, this configuration performs much better overall and the LTP current can now be increased to a more reasonable value (e.g. ~1mA per side).
Николай Евгеньевич, а какой в этом смысл? Я смотрел на характеристики, они вроде примерно одинаковые, при этом у LSK489 меньше паразитная емкость, а JFE2140 чуть меньше шумит.
Dear Nick, what's the point? Looking at the datasheet, the two parts are broadly comparable, the LSK489 has lower input capacitance while the JFE2140 has slightly lower noise.
Dear Nick, what's the point? Looking at the datasheet, the two parts are broadly comparable, the LSK489 has lower input capacitance while the JFE2140 has slightly lower noise.
LSK489 has offset 8 mV and noise 1.8 nV/sqrtHz, JFE2140 has offset 1 mV and noise 0.9 nV/sqrtHz , - much better for both OPAmps and PhonoPreampsDear Nick, what's the point?

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The DC offset is due to the difference in input currents and/or input impedances for a BJT input stage. However JFET's (unless a matched pair) will have a large intrinsic DC offset due to the large device variability in threshold voltages (BJTs are much tighter matched for Vbe) - discrete BJT probably lower DC offset than discrete JFET even with mismatched impedances, unless a monolithic matched pair is used. Even the LSK489 has 20mV worst-case offset, worse than many opamps which have the advantage of laser trimming and interdigitated layouts.I want it to have JFETs at the input to reduce current noise and get rid of issues such as DC offset (which is more or less inevitable with BJTs because of base current flowing through the biasing resistor).
If you manage to outperform an NE5534A in current noise, voltage noise, voltage offset and linearity you are doing well...
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I found jfe2140 (my favourite jfet atm) to be better matched than lsk489, in batches i got from mouser. And subjectively, better sounding.
After staring at the datasheets some more, I agree that the JFE2140 would be a better part in this application. It has lower guaranteed Vgs mismatch, and also a much more narrow Idss range, which means that I can safely set the current for the input differential stage at something like 10mA for better linearity and lower noise.
With a current-mirror load you can set the standing current very low and it will still be very well balanced.
Current mirror as a load of input stage add at least 3 dB noise [ https://www.patreon.com/posts/nezhelatelnost-86795812 ], reducing drain current also increases FET noiseWith a current-mirror load you can set the standing current very low

Do you have a simulation of that? A good input pair should be putting the signal above the noise floor of the next devices in the chain.Current mirror as a load of input stage add at least 3 dB noise
Such studies are published in the article by V.N. Maslennikov on page 90 of the "News of Tomsk Polytechnic University" 2007, volume 311, No. 4. I have the article on Patreon, here https://www.patreon.com/posts/nezhelatelnost-86795812 . The point is that the current mirror in the load is not a "subsequent stage", but affects noise in the same way as the amplifying transistors of this stage. [ https://c10.patreonusercontent.com/...XLxf6hnjLToJH_E3EfSN98=&token-time=1750377600 ]have a simulation of that? A good input pair should be putting the signal above the noise floor of the next devices in the chain.
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