Anybody tried building a discrete DAC seriously ?
Sorting my parts, I found 240 pieces of 200 ohm resistors.
TC < 5, standard tolerance 0,01%, individually tested for deviation from nominal value with resolution of 0,0001%.
Very tempting.
Sorting my parts, I found 240 pieces of 200 ohm resistors.
TC < 5, standard tolerance 0,01%, individually tested for deviation from nominal value with resolution of 0,0001%.
Very tempting.
Yeah, I've got one on the drawing board at the moment. Thinking of doing an R2R ladder with a Xilinx XC9572 front end. Still weighing up whether to direct drive the resistor ladder from the CPLD, or to use discrete buffers.
There is one project that has been published on the net, here. They produced a reasonable sound, I'm looking at something similar, but without the glue logic and long signal paths.
Really aiming for a proof of concept rather than something to listen to, but you never know.
There is one project that has been published on the net, here. They produced a reasonable sound, I'm looking at something similar, but without the glue logic and long signal paths.
Really aiming for a proof of concept rather than something to listen to, but you never know.
Oh, and another thing; 200R sounds a bit small. I was planning to use something at least two orders of magnitude more resistive. I guess it depends what you have driving it.
The problem may be to find zero ohm switches.
I did not think about it to much yet.
Another idea is to build a DAC only with transformers.
That would require the code for bipolar zero to be 0000000000000000 😕
I did not think about it to much yet.
Another idea is to build a DAC only with transformers.
That would require the code for bipolar zero to be 0000000000000000 😕
The low resistance switches are the other reason you'd want the ladder resistances to be high, so that switch resistance are not as significant.
I started a discrete DAC project years ago. Here is the concept (sorry, I had no motivation to translate on English):
http://www.freeweb.hu/tube/DDAC.html
At the bottom you can find the circuit diagram in PDF format, and some photos on the breadboard. I built one channel and it worked, but it was not suitable for any qualitative comparison.
I used 100k/0.01% 15ppm resistors in R/2R ladder arrangement. The switch is IRF7317 with 0.06 ohm Rds(on). In a ladder arrangement not the temperature coefficient is important, but the identical TC of the upper and lower element. This can be more easily provided. Even so, I used multiturn wirewound variable resistors for the 8 most significant bits. The bottom left part is for calibration of these bits. This part can be eliminated, if you use my alternative method:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=113620
The output part is just a sketch, I used a standard opamp analog output in the prototype. The deglitcher consisting of two cathode followers and a FET switch (and the input capacitance of the second CF) never worked; I wanted to control this sample&hold circuit from a STR1 derived signal reclocked to the master clock.
I hope someone gets inspiration from this.
Laszlo
http://www.freeweb.hu/tube/DDAC.html
At the bottom you can find the circuit diagram in PDF format, and some photos on the breadboard. I built one channel and it worked, but it was not suitable for any qualitative comparison.
I used 100k/0.01% 15ppm resistors in R/2R ladder arrangement. The switch is IRF7317 with 0.06 ohm Rds(on). In a ladder arrangement not the temperature coefficient is important, but the identical TC of the upper and lower element. This can be more easily provided. Even so, I used multiturn wirewound variable resistors for the 8 most significant bits. The bottom left part is for calibration of these bits. This part can be eliminated, if you use my alternative method:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=113620
The output part is just a sketch, I used a standard opamp analog output in the prototype. The deglitcher consisting of two cathode followers and a FET switch (and the input capacitance of the second CF) never worked; I wanted to control this sample&hold circuit from a STR1 derived signal reclocked to the master clock.
I hope someone gets inspiration from this.
Laszlo
As I review this old project, more details come into my mind. I used a 6V sealed lead-acid battery as the supply voltage of the MOS-FETs only. The FETs were mounted on PCB rails. There were very high peak currents through the FETs, probably because of overlapped switching (both the P-channel and N-channel FETs were ON for a brief moment). Now I would arrange 200k (2 x 100k in series) and 100k to GND, instead of 100k and 50k (2 x 100k parallel) to GND. I took the serial data (offset binary), bit clock and latch signals from the SAA7000 of a Marantz CD-74, it worked in NOS mode... The circuit can be simplified by using a single 74LS673 or 675.
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