Hi,
There is a discussion on a Chinese forum that the DIR1703 and AD1865 do not match without shift logic. Since the AD1865 data format is right justified, if I select the 16-bit right justified format for the DIR 1703 to capture 16-bit SPDIF, then all the AD1865 sees is 2 bits of 0s before the MSB. It would seem to work without shift logic. Will it work?
K K
There is a discussion on a Chinese forum that the DIR1703 and AD1865 do not match without shift logic. Since the AD1865 data format is right justified, if I select the 16-bit right justified format for the DIR 1703 to capture 16-bit SPDIF, then all the AD1865 sees is 2 bits of 0s before the MSB. It would seem to work without shift logic. Will it work?
K K
2707 i2s to ad 1862
hi can you help?
I have usb module from dddac that output a i2s and cd denon dcd-2650 with 4 ad 1862 , I want transformer in a usb dac 1862!
is possible?
hi can you help?
I have usb module from dddac that output a i2s and cd denon dcd-2650 with 4 ad 1862 , I want transformer in a usb dac 1862!
is possible?
Shifter
Hi nicoch46,
If I understand you correctly, you want to change a 16-bit I2S signal to a 20-bit right justified one. I think this might help:
http://www.geocities.com/nonospcm17...al_shifter.html
In this case, the data will be right shifted by 11 bit so that the 1862 sees the the last 20th bit as the MSB. I have simulated the logic in Pspice but have not tried it for real.
So can you get the 2707 in dddac to work ? Lucky fella. My own circuit has not been successful. Of about one thousand times I plugged in the chip, I have only one positive response from the computer. Other times the computer always return the messasge - device not recognised. I don't know if others also find the chip hostile.
Having read another post I think I can answer my own question in post #1. I will set the 1703 in 16-bit right justified mode and shift the latch clock by 2 bits. Then the MSB will align.
Cheers,
KK
Hi nicoch46,
If I understand you correctly, you want to change a 16-bit I2S signal to a 20-bit right justified one. I think this might help:
http://www.geocities.com/nonospcm17...al_shifter.html
In this case, the data will be right shifted by 11 bit so that the 1862 sees the the last 20th bit as the MSB. I have simulated the logic in Pspice but have not tried it for real.
So can you get the 2707 in dddac to work ? Lucky fella. My own circuit has not been successful. Of about one thousand times I plugged in the chip, I have only one positive response from the computer. Other times the computer always return the messasge - device not recognised. I don't know if others also find the chip hostile.
Having read another post I think I can answer my own question in post #1. I will set the 1703 in 16-bit right justified mode and shift the latch clock by 2 bits. Then the MSB will align.
Cheers,
KK
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