Digital attenuation for i2s

[fcserei]

I've succesfully connected a Philips cd player a to Behringer Ultracurve using I2s format (2*32 bits/sample) and clock sync.

The only problem the max digital output from the cd is about +6db DIGIMAX level for the behringer which overloads the EQ.
If I reduce the master level in the behringerit works fine, but I can not adjust the volume then.

I'm looking for a simple circuit or chip to attenuate the i2s signal by 12-18db with a simple bit shifting. The Behringer processes 24 bits, so shifting the input stream 2 bits seems to be no problem and Behringer shoul do something similar on the AES/EBU card, as the digit input card does not have this problem.

Can anybody help.

 

[Steve Eddy]

I don't understand. Are you saying that the I2S out of the CDP is sending greater than 16 bit samples?

se

 

[fcserei]

No. The player sends 16 bits i2s in 32 bit frames. The first 16 bit is cd data, then 16 zeros.
The behringer seems to attenuate the signal in the digital domain by 5db on the digital input (AES/EBU card), and 5db in the analog domain for the analog inputs to allow headroom for the digital eq, As I'm feeding the behringer after the A/D converters with digital signal, I have no attenuation, and overloading the eq.

What I need is a 12 db digital attenuator working with 32 bit i2s frames.

 

[steve jones]

Delay or shift WCLK by two bits should give you 12dB attenuation, provided that the Beringer will accept 18 bit data (or greater) .

 

[Steve Eddy]

No. The player sends 16 bits i2s in 32 bit frames. The first 16 bit is cd data, then 16 zeros.

Question. Where exactly are you plucking your I2S output from the CDP and how exactly are you determining that it's being sent in 32 bit frames?

The Philips I2S format is 16 bits left channel data, and 16 bits right channel data. Which decoder chip is your CDP using? And how do you you know what data format the Behringer is expecting to see out of its internal ADC?

se

 

[fcserei]

Delay or shift WCLK by two bits should give you 12dB attenuation, provided that the Beringer will accept 18 bit data (or greater) .

Sorry, but wrong. (Already tried - big noise).

The behringer uses 24 bits out of the 32. Let's say the input is
0011..11, after the 12dB attenuation the output with padding 0s at the end to have 24 bit data should look like 000011..11000000.

But for data beginning with 1, like 1011..11, the attenuated signal in 24 bits is 111011..11000000.


My logic design skills are a bit rusty now. Can somebody suggest a good TTL CAD package.

 

[fcserei]

Question. Where exactly are you plucking your I2S output from the CDP and how exactly are you determining that it's being sent in 32 bit frames?

The Philips I2S format is 16 bits left channel data, and 16 bits right channel data. Which decoder chip is your CDP using? And how do you you know what data format the Behringer is expecting to see out of its internal ADC?

se

i2s does not define how long is one frame, so you can have any number of padding bits after the data. 7210 uses 32 bit frames (that is what I tap for the signal), 7220 16 bit frames, newew chips (7345) 24 bit frames.

I've checked the data sheets for A/D, D/A used in the Behringer, checked the mode config pins, and found it is communicating internally with 11.289MHz master clock, 2.822 MHz bitclock and 32 bit long frames.

 

[guido]

Guess you need to make a nice drawing with all the signals.
And make one MSB bit into three..

Delaying signals can be done with a '74 FF, search for Guido and you will find an I2S splitter. I use one in this design to delay WS with one clockpulse (two sides of the FF delay each half a clockpulse).

This to know where the dataframe is in time and to inverse it (not inversing the other channel).

btw, it is now designed with one 4517 shiftreg and not the 8 TTL ones. Only 3 chips left, but i have some new idea's....

Regards,

Guido

 

[fcserei]

Never mind, I've solved it yesterday.
A couple of D flip-flops and a multiplexer - 2 chips. Working great. It was a big help to put down exactly what I need.

Now I have about 6 dB headroom for the eq and about 16 dB usable volume adjustment. With i2s input and 20 bit filterless DAC the Behringer is in an other league now.

If anybody interested, drop me a line.
Warning: not an easy surgery.

Thanks

 

[rfbrw]

How do you deal with the sign bit ?

ray

 

[fcserei]

I made two shift registers out of the d flip-lfops (74..174) samling at positive edge:

a 3 stage to delay the word select (W0 is the original, W1 delayed by 1 clock cycle , W2 and W3)

a two stage to delay data (D0, D1 and D2)


The data output is always D2 except:

D0 when (W0=0 and W2=1 and W3=1) or (W0=1 and W2=0 and W3=0 )
D1 when (W0=0 and W2=0 and W3=1) or (W0=1 and W2=1 and W3=0 )

In this way I hold the sign bit for 2 more clock period then output the delayed magnitude bits.

I use a multiplexer (74..151) to make this selection. Working fine and does not alter the jitter crirical Word select.

 

[rfbrw]

Don't quite see how you hold the the sign bit in position and delay the other bits relative to it. For instance how many shift registers do you have in total ?

ray

 

[fcserei]

Don't quite see how you hold the the sign bit in position and delay the other bits relative to it. For instance how many shift registers do you have in total ?

ray

WS --> Delay ----->Delay ----->Delay ----->W2
| |
| ----------------->W1
|
----------------------------------------------->W0


Data--> Delay ----->Delay -------------------->D2
| |
| -------------------------------->D1
|
----------------------------------------------->D0

Then I use a mux co combine the signals according to the logic above.


This way the data is:

MSB MSB MSB MSB-1 MSB-2 .... LSB

instead of

MSB MSB-1 MSB-2 .... LSB

 

[Pulse-R]

does this mean this technique could be used to implement a 'digital volume control'?
if so, would be much easier than what I had planned...

still not quite understanding the logic though

 

[macboy]

does this mean this technique could be used to implement a 'digital volume control'?
if so, would be much easier than what I had planned...

Yes, but with coarse 6 dB steps. And the more attenuation you want, the more logic you need to get it. Plus the logic to select 1-of-N attentuation levels. It gets messy fast.

still not quite understanding the logic though

You need to understand the 2's complement representation of signed integers. Look it up in Wikipedia if you have to.
In 2's complement, 1 is 1, 0 is 0, etc., but -1 is "all ones", so for a 16 bit number, -1 is b11111111. Since -2 is -1 subtract 1, it is b11111110, and -3 is b11111101, etc. Note that the most significant bit becomes the sign bit (1 for negative, 0 for positive).

Consider the represention of -1 as a 12 bit number. It is b111111111111. So how do you convert an 8-bit -1 to a 12-bit -1? Well, you can't pad it with (12-8= 4) zeros, because then you get b000011111111 which is +255. And you can't just pad it with 4 ones because then a positive number becomes negative. Instead, you need to copy the sign bit 4 more times.

In fcserei's system, each channel uses a 32-bit 2's complement number per sample. The 16 MSbs are used for the 16 bit samples, with the 16 LSbs essentially unused. To attenuate the samples, he shifted the 16 bits some amount toward the LSb side (by delaying the word clock). To maintain proper 2's complement signage, he then needed to duplicate the sign bit and fill it into the 2 new MSb bits prior to the 16 bit data.

 

[Pulse-R]

ah, ok

yes, 6dB is a bit coarse...
back to my drawing board....
I have made a design schematic for a 16/44 - to - 24/96 converter with variable attenuator, but I am not good at PCB design... that will take longer