It's all in the datasheet. Not too tricky to read, but I admit its fairly long.
If OP needs help on implementation, happy to advise, but as you said this seems to be a bottomless pit?
16bit I2S has to be explicitly defined when BCKIN is 32Fs. The PMD100 doesn't do I2S.
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PMD100 does 16 bit right justified or "up to 24 bit" left justified. Copes with anywhere from 16 to 24 bits without any changes. It can do I2S, but only if you introduce a 1 bit clock clock cycle delay between the word clock and the data input to handle the I2S offset.
