dead time, and class D distortion

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fokker said:


how could it be that the UcD is following the lowly Philips on DT adjustment? didn't the wise say that that is only the DT in the "weakest possible sense"?

apparently, the UcD folks also like the "weakest possible" DT adjustments. I wonder if they will ever offer something better than the 'weakest possible" DT adjustment in the next revision.

🙂


Well you see they know how to select or rather design the components of the surrounding circuitry in order to get themselves to a point where a weak... or simple .. fine tune adjustment is all that's required.

You don't because you also fail to realize that design is a process that doesn't envolve blindly swapping parts that everything gets designed around like the drivers, which is actually the reason why I pointed out to you that it's a weak means of adjustment in the sense of your total reliance of one particular method that's simply a fine tune on one particular circuit.

In contrast I believe someone made the statement the surrounding values on the philips note were really only good for the components they selected. If you use your own selections, everything changes, more so if you don't have a clue what the hell application specific means at the level of electronics to which you're attempting to work. The parameters in question are defined by design.
 
phase_accurate said:


I assume the main deadtime is already implemented (and properly dimensioned) in the driver stages and this one is just used to fine-tune production tolerances.

Regards

Charles


Pafi said:


Not really. If this was the reason, then it would be much less sensitive to dead time. 0,6...1V for a 1...5% of cycle is nothing, especially since this would be constant if you were right. Constant deviation from ideal for a constant time cannot cose nonlinearity.

The problem is much worse, and egsists even with ideal switches and ideal diodes. There is five domain: "ZERO": if inductor current is between -peak and +peak of ripple, then output current in the moment of switching off is on the normal direction for the actual MOSFET, so voltage is immediately changes to the other rail. If we calculate average value of output voltage for a cycle, we find that it doesn't differ from ideal, because there is a positive and a negative deviance as well. But there is a different domain: "POS" If inductor current is higher then ripple peak, then voltage is constantly sit on negative rail during both dead times (there is 2 in one cycle). Average voltage differs -Vcc*2*dead time/Period from ideal. At output current of less then -peak of ripple ("NEG") the situation is the opposit of "POS", voltage is more then ideal for same amount. You can see this on IVX's picture.

But what if output current is equal to +peak of ripple ("POS BORDER")?

To be continued...


What if you only switched when inductor current was crossing zero.... in a single cycle hysteretic converter. Deadtime constraints would be greatly reduced due to being free from the syndrom arguably described as hard switching.

Peak Idle current could also be made adjustable, if not smart, to further immunize it against poor efficiency at low output power.

Differences in overall delay are inherently corrected for in self oscillating amps as well. Seems like the simplest compete solution, solide overcurrent protection is already built in as well. You'd be able really push the switching frequency higher too.
 
Actually, there are not reason to have minimal dead time at <10W region (of course approximately -depends from inductor, load impedance and rail voltage) output power, so we can reduce idle consumption by modulating dead time (e.g. 100nS idle to 20ns loaded). BTW, i see no logic when reading -"special technique called nano alignment effectively removes dead-time distortion" at 1 W, or -"you can see dead-time distortion as a rise in THD levels at 5-7 kHz".
 
Actually, there are not reason to have minimal dead time at <10W region (of course approximately -depends from inductor, load impedance and rail voltage) output power, so we can reduce idle consumption by modulating dead time (e.g. 100nS idle to 20ns loaded).

Apart from the fact that in most cases the distortion behaviour below 10 Watt is more important than above - why not precompensate the signal in order to minimise distortion - and leave deadtime constant ?

This wouldn't be easy, I know. Particularly because deadtime-distortion is depending on output CURRENT which by itself isn't necessarily always proportional to output voltage.

Regards

Charles
 
Not easy, maybe, because even output current isn't exact point, when small signal linearity will break. Modulated dead time will allow to achieve better efficiency at low power region, or comparable efficiency on the musical signal with lower THD.
For example:
UcD400@factory_idle@5W=.005% THD
UcD400@more_idle@5W=.003% THD
UcD400@factory_idle@80W=.018% THD
UcD400@more_idle@80W=.005% THD
PS: 80W@1KHz/8Ohm=-3db
 
darkfenriz said:

If slew time were lower, than the actual dead time should be higher to avoid cross conduction, right?

What do you think such a discrete half bridge mosfet driver works like?
It seems to me, that it could give both high slew, resonable dead time and low conduction losses. I am just beggining to learn though.

best regards

Hi Dark,
yes for very fast slew rates ( = low slew times) I would prefer some more dead to prevent my calm sleep in the night.
But we can look slightly more detailed. What is causing poor precision of dead time?
a) Instable values in dead time generator.
b) Slow slew.
Especially in case a) you have to take care. Better not combine a poor dead time generator with short dead and fast slewing.
Situation b) is less critical. If precision is poor because of slow slewing, it might be worth to try faster slewing. On one hand you make the system more critical, but you gain precision.
In my case with the accurate IR driver I am thinking about exactly this. I might speed up the slewing to the allowed limit of my MosFets (5.5V/ns) and also speed up the turn OFF.... still not finalized.. Besides distorsion I have another reason for this. The IR driver has a fast shut down, which acts immediately if 200ns after the driver output turns to HIGH. It is measuring the Ugs of the switch, means if my switch is not fully in the state of low impendance the voltage drop at high loads might cause undesired shut down. So I do not feel comfortable with a length of more than 100ns for my Miller plateau.

Uuhhhgs. Discrete driver. I only used some PNPs to speed up the pull down in my boost converter but never experimented with a complete driver. In your schematic I would be concerned about the turn OFF delay of the first PNP. You drive this BJT into heavy saturation, so it will need long time for it to turn isolating again.
I remember that I measured in an similar arrangement (but was NPN) roughly 800ns turn OFF delay. 2N2222 and base-emitter resistor of 1k. Unfortunately I do not remember the load and also not the overdrive factor.
You can improve it by anti saturation diodes as in the attached scetch. It limits min Uce to the value of Ube.
For D2 it might be an improvement to use a schottky, if you take care for a type with low junction capacitance. Also take care for the voltage rating of D2. The 1N4148 is only suitable if you use low rail voltages.
 

Attachments

http://ece-www.colorado.edu/~rwe/papers/CIT82.pdf , fig. 5,6,7

This is a different type of distortion. Here isn't dead time, but switches have a nonlinear forward voltage drop. This nonlinear voltage affects output during the whole cycle. Mosfets don't have nonlinear forward voltage (OK, this is only an assumption, but quite good on typical conditions), so distortion can arise only when they don't control fully output voltage (eg. during dead time).

Compare Vout vs. Vin curves in this paper, and on IVX's simulation! You can see clearly the difference.
 
phase_accurate said:


I assume the main deadtime is already implemented (and properly dimensioned) in the driver stages and this one is just used to fine-tune production tolerances.

Regards

Charles

and you may well be right on that. However, unless we know precisely what Hypex did, it is a undisputable fact that that little resistor changes deadtime, which is precisely what Phillipse said in that application and what we are talking about here.

until people start talking about but unable to define "application specific" dead time control, 🙂
 
This is my simple test circuit, which i used for fig. "PWM linearity", but it seems, that 3D plot is much more informative! Y -THD logarithm scale (15db=.05%), X -input sine voltage (Gain=8.3, so 6V is almost clipping), Z -THD analyze bandwidth (2k-24k). 25% opacity are 100ns dead time plot, 100% -10ns. 100Khz switching, not so typical, but 4-5x faster rendering. Up to ~20W THD in the both case have relatively low difference (~2/3 times for 1/10 dead time!), and 6 times for >20W.
 

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Hi Ivan,
that's a cool simulation!
In your circuit you are ramping something like +/-4.15Apeak HF ripple.
We can see that the THD is nicely low as long as the peak currents of the load do not exceed something like 3A (1.5V x 8.3 / 4 Ohms).
Above this the dead time is starting to have a massive influence...
Really cool. And fortunately with results that match more or less to my imagination. ...so I do not have to scramble my entire current brain model...

Thanks for your simulation with similar values to my planned design!!!
 
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