I also developed a pretty simple circuit for doing I2S -> +/- I2S. It can be synthisized in about 120 macrocells, though if you're only doing 16 bit audio you cut down to 104. It can be done more efficiently but I wanted something easy to do w/ no freaking counters to debug so I use a 64-bit shift register to capture an entire sample, even the bits I don't need.
Input is normal 32-bits-per-sample I2S from a crystal chip and output is the same, with positive on the left chanel and negative on the right channel.
The output bitclock is the input bitclock inverted, though this could be shifted back by another half-bitclock so it was in phase again, if you really wanted it to.
The output wordclock is delayed by a half-bitclock (or would be a full bitclock if you in & out BCLK to be the same...).
I guess I'd recommend reclocking the output with the master clock as I don't think CPLD's are all that reliable jitter-wise. Maybe not such a problem if your DAC transitions on the bitclock, but definitely would have to be reclocked if it transitioned on the word clock, imo.
The problem currently is the only available 128-macrocell CPLD in a remotely usable package is from Atmel who wants you to buy thier software to program thier stuff (unless you use archaic CUPL language).
Xilinx is good stuff but would need 2 chips as only the 64-macrocell versions are available in a hand-solderable pitch. Though two of the XPLA 3 3.3v 5-volt compatible 64-macrocell guys would do it, and they are available in PLCC packages. EDIT: Actually maybe they aren't available any more...
Input is normal 32-bits-per-sample I2S from a crystal chip and output is the same, with positive on the left chanel and negative on the right channel.
The output bitclock is the input bitclock inverted, though this could be shifted back by another half-bitclock so it was in phase again, if you really wanted it to.
The output wordclock is delayed by a half-bitclock (or would be a full bitclock if you in & out BCLK to be the same...).
I guess I'd recommend reclocking the output with the master clock as I don't think CPLD's are all that reliable jitter-wise. Maybe not such a problem if your DAC transitions on the bitclock, but definitely would have to be reclocked if it transitioned on the word clock, imo.
The problem currently is the only available 128-macrocell CPLD in a remotely usable package is from Atmel who wants you to buy thier software to program thier stuff (unless you use archaic CUPL language).
Xilinx is good stuff but would need 2 chips as only the 64-macrocell versions are available in a hand-solderable pitch. Though two of the XPLA 3 3.3v 5-volt compatible 64-macrocell guys would do it, and they are available in PLCC packages. EDIT: Actually maybe they aren't available any more...
Altera MAX7000 CPLD family provide device up to 256 macrocells and you can download free software from Altera's website.
For those using programmable ICs to have +/- I2S, is it also possible to implement oversampling? Or are the chis not fast enough?
FYI. The normal pin to pin delay is 10ns max for Altera MAX7000. It's fast enough for oversampling application. If you want to use a 100MHz OSC for reclocking, you may need to buy faster version with delay 5ns, 6ns or 7ns.
I see a lot of general interesting inputs, but I would like to ask every one to stay on-topic on my thread. Please refer to my original post at the beginning...
Every one with some good ideas, but still off-topic, should open his or hers own thread please.
To re-cap: I have asked inputs on 2 possible pcb grounding ideas with local power supplies for the chips, plus some questions on parts values.....
thanks !
doede
Every one with some good ideas, but still off-topic, should open his or hers own thread please.
To re-cap: I have asked inputs on 2 possible pcb grounding ideas with local power supplies for the chips, plus some questions on parts values.....
thanks !
doede
The first option but with the ground plane second layer like a shield. Conect Agnd and Dgnd of CS directly.
thanks pedja,
why would you prefer to share the return path to the battery for VD and Va?? any specific reason?
tc
doede
why would you prefer to share the return path to the battery for VD and Va?? any specific reason?
tc
doede
Dear Doede,
Sorry about off topic. I would like to say thanks to you here because most of the valuable information I got about 1543NOS DAC is from your website. It's very clear and convincible
BR
Vincent
Sorry about off topic. I would like to say thanks to you here because most of the valuable information I got about 1543NOS DAC is from your website. It's very clear and convincible
BR
Vincent
I find the discussion regarding grounds and PS lines in this thread http://www.diyaudio.com/forums/showthread.php?s=&threadid=30043&perpage=15&pagenumber=3
particularly educating. This actually led me to changing my TDA1543 DAC layout from common ground plane to separate ground return paths, with ground plane in top layer and only chips ground pins connected to it.
I think that's more proper way to do that.😉
particularly educating. This actually led me to changing my TDA1543 DAC layout from common ground plane to separate ground return paths, with ground plane in top layer and only chips ground pins connected to it.
I think that's more proper way to do that.😉
Pedja said:
Hi pedja
Actually they are TL431 shunt regulators.
The picture is not so clear I realize (max resolution allowed by the forum
)tc
doede
Hi Doede,
Yes, I see now the explanation in the bottom left corner.
The goal is to keep the voltage difference between two CS Gnd pins as small as possible.
Consider the benefits of usage of separate regulators, they divide the input and output loop. In that regard, the input loop current flows back to the battery, no reason to send this current via TDA.
Once you determine both the current paths and real world dimensions, it is not bad to make some compromises with the star ground concept.
Pedja
Yes, I see now the explanation in the bottom left corner.
The goal is to keep the voltage difference between two CS Gnd pins as small as possible.
Consider the benefits of usage of separate regulators, they divide the input and output loop. In that regard, the input loop current flows back to the battery, no reason to send this current via TDA.
Once you determine both the current paths and real world dimensions, it is not bad to make some compromises with the star ground concept.
Pedja
- Status
- Not open for further replies.