I have recently been informed that page 1 of the DACMagic schematics is missing from the zip file, and page 2 appears to be duplicated. I'll upload/link to the missing page as soon as i can get hold of a copy.
I2S signal for dual TDA3105 DACs
Reviving an old thread - links are dead...
I managed to find the schematic diagram for the D/A and analog sections, see below. However, CA does create balanced output from a single TDA1305, one for each channel. This means they need to do something special with the I2S signal, and that a standard I2S output with L/R data will probably not work. This is bad news as I would like to connect a PBPi as media streamer to it.
I have just started looking into this but in short the problem is that I do not understand how the designers at CA (John Westlake) have done this exactly. They use 2 separate data lines, one for each DAC chip (L/NOT_L and R/NOT_R, resp.) with the data for both balanced, symmetrical channels somehow split and inverted. These are synchronized over a single Word Select line and master clock.
Could somebody enlighten me how this is done and what the I2S signal should look like?
Would be really grateful for a link to the service manual, or schematics of the digital section as well!
Reviving an old thread - links are dead...
I managed to find the schematic diagram for the D/A and analog sections, see below. However, CA does create balanced output from a single TDA1305, one for each channel. This means they need to do something special with the I2S signal, and that a standard I2S output with L/R data will probably not work. This is bad news as I would like to connect a PBPi as media streamer to it.
I have just started looking into this but in short the problem is that I do not understand how the designers at CA (John Westlake) have done this exactly. They use 2 separate data lines, one for each DAC chip (L/NOT_L and R/NOT_R, resp.) with the data for both balanced, symmetrical channels somehow split and inverted. These are synchronized over a single Word Select line and master clock.
Could somebody enlighten me how this is done and what the I2S signal should look like?
Would be really grateful for a link to the service manual, or schematics of the digital section as well!
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Schematics for Dacmagic 2 / DAC3 / CD6
Following up on my previous post: I contacted Cambridge Audio support for a service manual for the Dacmagic 2/DAC3. Initially they could not help me as the unit was designed in the previous century. However a request to the engineering department brought up some schematics, also for the CD6 which has a very similar DAC section.
All is clear now, a 'normal' I2S signal is coming from the receiver chip (TDA1315) that should be useable for cummunication.
For anybody interested in these units: I will upload the schematics to Hifiengine.
(Note that these are revision C and have some manual corrections that are included in the rev. D for the analog part that is available from the Elektrotanya site.)
Via this way I also want to say a big thank you to Tom Castle from Cambridge Audio for his support in tracing the old schematics. Highly appreciated!
Nijs
Following up on my previous post: I contacted Cambridge Audio support for a service manual for the Dacmagic 2/DAC3. Initially they could not help me as the unit was designed in the previous century. However a request to the engineering department brought up some schematics, also for the CD6 which has a very similar DAC section.
All is clear now, a 'normal' I2S signal is coming from the receiver chip (TDA1315) that should be useable for cummunication.
For anybody interested in these units: I will upload the schematics to Hifiengine.
(Note that these are revision C and have some manual corrections that are included in the rev. D for the analog part that is available from the Elektrotanya site.)
Via this way I also want to say a big thank you to Tom Castle from Cambridge Audio for his support in tracing the old schematics. Highly appreciated!
Nijs