As there were a few questions about this device in the OPA1656, I figured I would start a new thread.
The TI precision DAC team recently released the DAC11001A, a single-channel, unbuffered, R-2R DAC.
Info available at:http://www.ti.com/product/DAC11001A
Here are some highlights of this DAC:
We found some interesting needs for a device like this in control systems and arbitrary wave-form applications, where excellent DC performance was required, as well as good dynamic behavior. The device features a robust sample-and-hold subcircuit that removes code-dependent glitch behavior.
We thought it would be fun to evaluate the device for audio applications, as there are some audio designers and enthusiasts that still want that R-2R architecture 🙂
I am working on releasing an audio reference design, but that will probably be online in Q2-2020.
The TI precision DAC team recently released the DAC11001A, a single-channel, unbuffered, R-2R DAC.
Info available at:http://www.ti.com/product/DAC11001A
Here are some highlights of this DAC:
- 20-bit monotonic: 1-LSB DNL (max)
- Integral linearity: 4-LSB INL (max)
- Low noise: 7nV/√Hz
- Code independent low glitch:
1 nV-s - Flexible output ranges: VREFPF to VREFNF
- Integrated, precision feedback resistors
- Excellent THD: –105 dB at 1-kHz fOUT
We found some interesting needs for a device like this in control systems and arbitrary wave-form applications, where excellent DC performance was required, as well as good dynamic behavior. The device features a robust sample-and-hold subcircuit that removes code-dependent glitch behavior.
We thought it would be fun to evaluate the device for audio applications, as there are some audio designers and enthusiasts that still want that R-2R architecture 🙂
I am working on releasing an audio reference design, but that will probably be online in Q2-2020.
First question:
Note that the first version released is the DAC11001A, the next version will achieve tighter INL and drift specifications.
The sample-and-hold circuit improves the AC performance of the R-2R by making the glitch code-independent. This removes some of the nasty harmonics that you might see in a regular R-2R design.
The I2S to SPI is a bit of a problem. Fortunately, the DAC11001A features a daisy-chain mode that looks somewhat similar to I2S. I was able to create the glue logic that converts 24-bit, right-justified I2S to SPI using only 2 flip-flops, a shift register, and 7 logic gates. When I post the reference design I will share the digital logic sims.
To be clear, this device was not designed for audio but rather very high-end test and medical applications. R-2R DACs in audio is a bit of a niche application. That being said, there are some companies and hobbyists that are using R-2R DACs still (Schiit's Yggdrasil, for example).
Note that the first version released is the DAC11001A, the next version will achieve tighter INL and drift specifications.
The sample-and-hold circuit improves the AC performance of the R-2R by making the glitch code-independent. This removes some of the nasty harmonics that you might see in a regular R-2R design.
The I2S to SPI is a bit of a problem. Fortunately, the DAC11001A features a daisy-chain mode that looks somewhat similar to I2S. I was able to create the glue logic that converts 24-bit, right-justified I2S to SPI using only 2 flip-flops, a shift register, and 7 logic gates. When I post the reference design I will share the digital logic sims.
An externally hosted image should be here but it was not working when we last tested it.
If I would need to promote a new R-2R DAC I would avoid quoting the Schiit Yggdrasil as an example. That implementation is a disaster (nothing new from Schiit, though). I'm sure the schiitters will debate this 😀.
Review and Measurements of Schiit Yggdrasil V2 DAC | Audio Science Review (ASR) Forum
That's largely an irrelevant question, an R-2R DAC can be made much better than the resistor absolute precision would allow in a brute force approach. The data sheet linearity spec has the relevant data.
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Sounds great ! Low noise voltage regulators from TI and why not from AD (like the LT3042) should be useful in this kind of project...
I say a nice addition to the community, and I say that as an AKM fan, so...
Thanks for all your efforts and for sharing them, to my ears at the end only the sonic vertues matter, let's see how that one performs
Subscribed
Claude
Thanks for all your efforts and for sharing them, to my ears at the end only the sonic vertues matter, let's see how that one performs
Subscribed
Claude
I'm sure TI doesn't expect to sell many to the audio market. As long as the datasheet doesn't claim superior sound quality, more power to them. If people want to pay $50+ for a converter that's worse for audio than PCM179x then I guess they can.
It seems the maximum output sample rate is 400 kHz if I read the datasheet correctly?
I'm not sure this will work all that well for anything above 44.1/48 kHz sample rates if so. As I am sure you are aware, most audio converters operate at 8x Fs with an interpolation filter so that the analog filter requirements are relaxed. Do you plan to implement a digital filter in the reference design at all?
PCM1704 would be the target to beet and spline interpolation at x MHz as WADIA did 😱
Hp.
The device can support about 1MSPS, but there are some caveats. The main thing to remember is that this device has a track-and-hold implemented that helps with the glitch. By default, the device samples for ~1.5 µs, then releases. This removes the R-2R glitch (but add some other, smaller glitch). Now the output needs to settle to the final value. If you update too quickly you will prevent the output from settling before the TnH engages again. If you shorten the TnH timing, then you will see more glitch.
We have a few registers that let you play around with the TnH timing, a code step threshold for enabling it, as well as just disabling it altogether. For a specific sample rate you might need to play with the values a bit to find a good compromise in performance.
The reference design features an XMOS controller that allows 192ksps data from being streamed to the device. If you provide 192ksps audio, then it will not implement any interpolation.
In the first prototype, I used the PCM5142 in external filter mode, which will interpolate any input to about 384ksps. This was pretty fun because you could implement the miniDSP anyway you saw fit and it was able to provide some nice audio features, like soft mute, volume ramps, clock error detection, etc. Ultimately I removed it because I felt that it over-complicated the design as I needed an MCU to configure the PCM at startup.
My reference design will be characterized at 48ksps, 96ksps, and 192ksps. I might do a few tests at 384ksps as well, but that will require me to use a different source.
We have a few registers that let you play around with the TnH timing, a code step threshold for enabling it, as well as just disabling it altogether. For a specific sample rate you might need to play with the values a bit to find a good compromise in performance.
The reference design features an XMOS controller that allows 192ksps data from being streamed to the device. If you provide 192ksps audio, then it will not implement any interpolation.
In the first prototype, I used the PCM5142 in external filter mode, which will interpolate any input to about 384ksps. This was pretty fun because you could implement the miniDSP anyway you saw fit and it was able to provide some nice audio features, like soft mute, volume ramps, clock error detection, etc. Ultimately I removed it because I felt that it over-complicated the design as I needed an MCU to configure the PCM at startup.
My reference design will be characterized at 48ksps, 96ksps, and 192ksps. I might do a few tests at 384ksps as well, but that will require me to use a different source.
Paul, are you aware that you could use two dac11001A chips to make a Sign Magnitude DAC, which would be a great advantage for Audio use ?
Btw, the DAC11001A datasheet often crashes my Adobe Reader, and yes, it's an old version 8, but I like that version....
I considered using two DACs per channel, but in the end, I felt it would just over-complicate the reference design. Though digitally inverting one of the DACs would not be very complicated.
For audio these DAC's require a heroic de-glitcher, we learned this in 1988 already. Otherwise you get schiit.
It is not for me to say if the de-glitcher in the DAC11001A is heroic, but I can say that our designers put a heroic effort to make it as good as it is.
We spec'd our glitch as 1nV-s for all codes, which helps with THD!
We spec'd our glitch as 1nV-s for all codes, which helps with THD!
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Since no one has a suite of audio measurements for these R2R DAC's I guess I will have to wait and see. I see a spec of -105dB, I know a 20bit R2R is capable of <-120dB with an external de-glitcher.
Not for long, my demo board and the associated controller are on the way from DigiKey. They'll have to wait until they'll find a place in the project queue, and next week I'm away in the Bay Area for business, anyway.
The TI 20bit SAR ADC and this R-2R DAC will make an interesting SPI pair 😀. I already measured the TI SAR ADC and is around -123dB.
