DAC I/V measurements

Conclusion

What makes it even more remarkable is that it is a "zero-feedback" design with lower THD(+N) than high-specification op amp with feedback. Kudos to @smms73!
The circuit has very high NFB current feedback by the collector of Q19 to the input. The very high gain is due to the impedance of the CCS Q7.
final_2.png

These measurements are very valuable to those who design IV stage.
 
  • Like
Reactions: tonimxp
PMD100 datasheet contains examples of how to feed I2S to PMD100 from different source devices.
As I already replied to you on another thread you should also check that the system clock (MCK) for PMD100 is either 256fs or 384fs. Some USB-I2S boards (including Amanero) use 512fs MCK which does not work with PMD100. If you have an oscilloscope you should check the frequencies of LRCK and MCK.