CS8420 Schematic can you double check?

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Not having explained what you want to do, and with no component values, it's hard to say how many errors you *might* have on this schematic. ;)

Which hardware mode did you *want* to use? The schematic shows you're setup for hardware mode 1 with the default data flow, with AES3/SPDIF input. You don't have DC blocking caps on the pulse transformers, and I'd recommend adding those.

I presume you're using TLV431's for the shunt regulators- output bypass cap quality is important, so select them carefully. I've usually found it desirable to use OSCON's in combination with large and small MLC's, to stagger the resonsances and impedance.

Presuming you're using a standard 44.1 kHz input, the standard values for slow setting PLL will work fine. If you want to lock onto 88.2 or 96 kHz for the purpose of de-jittering, then you should use the fast values.

What output sample rate are your intending to use- this dictates your master clock frequency.

The CS8420 Evaluation board document is a good source of "how to" for experimenting with the 8420- get it here.

Have fun with your project.

Best Regards,

Jon
 
hello,

The target is hardware mode 1 with Spdif in and uppsampled spdif out aswell as a datastream to the dac chips in OF3 (right justified 24bit) the dac will be an cs43122 but i would like to test the cs8420 card first before buidling the dac card.

I dont see any reason for using a cap att the input to break dc since the cable is short ande the sorce known.

i didnt write the resistor values since im not concearned about them its mainly the pull upp and down resistors and TCBL, COPY ORIG thats giving me a headache...

btw thanks for yout input.
 
Yes, going through the data sheet and double checking the pint assignments for the right hardware mode is something of a pain.

You may already have the parts you've drawn in for your reset generator, but why not use one of the single chip devices like an Analog Devices ADM709? This is basically an upgrade on the Maxim 709. It's available in an 8 pin package which is not so hard to work with manually as the Fairchild reset devices which are in SOT23.

Your project is pretty similar to one I've been working on, but I'm cheezing out on the this one and using a CS4397.

Next version will probably use the PCM1738 so I can do a discrete I/V and buffer; my current one uses a discrete non-feedback output buffer with transformer coupling from the differential DAC outputs.

Regards,

Jon
 
Your schematic looks fine to me as far as the configuration for Hardware Mode 1. In my case, I'm using master clock for sample rate doubling to 88.2 kHz.

Right now I'm just working out the details for the 1738 "proposal"; I'm not sure that I would use it with a 1706 externally; the 1738 does have the sharp and slow roll off modes, but it may be easier to setup or better performing with the 1706.

I'm probably going to purchase the evaluation board for the 1738 later this summer, since I can strip out their analog section and make a small breadboard to test my own I/V circuits with it before comitting to a PCB. Simulation is one thing, but even with good device models, there's nothing beats the real world! ;) The "slow" filter setting in the BB/TI digital filters sounds quite nice; Ayre offers it in the D1 and the new CX7, and I think it is important to their final sound.

This project is being done in a modular fashion- the 8420 "reciever" board is a sepearte piece. The analog ouptut buffer is also. These don't need to be 4 layer boards, but I think the main converter board will have to be for best performance (even though the Burr Brown eval board appears to be a two layer from their documentation).

When I have something complete enough (and tested to some extent) to feel comfortable sharing, I would have no problem doing this. Many times the best of ideas still needs some work in development and refinement. The "just average" ideas need even more work!

Regards,

Jon
 
I'm helping a friend's son get tires for his car tonight, it looks like- (just found out!), but I'll look at this soon (probably on the weekend) and give you my comments.

Oops, you may have a problem with your "zipper"; WINZIP reports this is not a valid archive file. Try again and I will check it out. What design tools are you using? I use the Protel Design Explorer system.

Regards,

Jon
 
The extractor reports there are no files to extract. Did you have a file name extension on the file you created? Is it a Photoshop PSD file, or did you save to a jpeg?

Anyway, still no luck getting a file out.

BTW, there are some freeware/demo PCB packages that you could download- have you thought about doing that for creating your design? Then you have have a schematic with true netlisting and DRC. There's a European outfit I use for personal PCB's, they have a lot of downloads and links; plus there's the demo version of Proteous; you might find those interesting.

PCB Pool

Regards,

Jon
 
You can email it to me directly; that's OK with both my email systems.


The use of seperate regulators, such as the TLV431, for the digital and analog 5V supplies hasn't been a problem for me with either the CS4390 or CS4397; I use the "high grade" versions, and 1% resistors, of course.

I also recommend using OSCON caps for the electrolytic local bypass, in addition to stacked film and ceramic for HF bypass. The best results have been with the larger MLC ceramic caps such as used for CPU VRM bypass caps; these are low impedance, low inductance, and only have price as a drawback- and they're readily available (in the states) from Digikey and others.

Regards,

Jon
 
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