CS8412 or AD1892?

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Marlowe

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Joined 2003
cynicalaudio.blogspot.com
#1
Hello everybody,

Thank Peter Daniel, jean-paul, Elso Kwak, and other guys. I built a simple DAC with CS8412 and TDA1543 on last week.
However I think the jitter of CS8412 is not very low, so I want to do something to decrease it. I have two ideas currently:
1) adding a reclock circuit between CS8412 and TDA1543 or
2) replacing CS8412 by lower jitter digital receiver as AD1892.

What is the choice more worth to try?

Thanks.
 
#2
AD1892

Hi,
I've built a DAC w. 1892 Receiver/SRC, and had no troubles with it up to date. I have not used 8412, but maybe if you try them, better go for the new CS8415A and CS8416. The jitter of the output stream of the AD1892 should be equal to this of the clock, according to datasheet. I have no comparision between different receivers although. I had a question here about the CS8416 vs DIR1706 Receivers, and the two answers generally says "CS8416".
More, AD1892 decodes "only" 20 bit audio, and max 50kHz SR. This is the case w. CD's. I use it with AD1852 companion.
Regards,
Kaloyan
 
#4
Marlowe
Here there is a compromise. AD1892 will rescue you from jitter, but you will get in exchange other problem. This problem is the digital filtration, which will kill all of charm 1x oversampling.
Besides, AD1892 requires the external precision generator, in the other case, jitter will remain.
AD1892 requires external microcontroller for configuration of outputs mode.
Differently, without the microcontroller, by default, output mode is Philips format, but data resampled full to 20bit. You will lose 4 bits with yours TDA1543.

machinow
I had a question here about the CS8416 vs DIR1706 Receivers, and the two answers generally says "CS8416".
Click to expand...

Why so, have they told?
Where can I look this discussion?

Regards
halyavshick
 
#5
External clocking of the 8412 ???

Good idea !! I just had the same idea 🙂 and made a quick design.

I will build this in the next week, but you can try it allready if you like.

Good luck !

Doede
 

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#7
Hi !

Actually I do it in Asynchrone Mode. I have done this befor with the CS8420, worked absolutely fine and gives a better result than when the clock is retrieved by the receiver (through the internal PLL)

I know some people, say that asynchrone clocking is just resampling and as there is some "phaseshift" therefore jeopardizing the signal. But, as said, I have tried both and the results were very nice... Plus the effect of the Drive and SPDIF cable was minimized as the clock is redoing the whole thing....

Doede
 
#8
Hi!
Whether you noticed "metal shades" in a sound at use 8420?

about CS8412...

Actually I do it in Asynchrone Mode
Click to expand...

The clock of transport and dac should be equal, but there is a disorder of parameters always (which is marked in ppm), therefore, in this case, there can be errors in the data.

Datasheet:
If the circuit generating SCK and FSYNC is not locked to
the master clock of the CS8412, the serial port
will eventually be reread or a sample will be
missed.
Click to expand...
Therefore it is desirable clock from the dac module`s oscillator to submit to CD-transport by a separate link.
 
#9
RECALL of the CIRCUIT above !!!!!

Sorry guys, I need to recall the circuit posted above :cannotbe:

The circuit itself is not the problem, I just used the wrong binary counter. I misjudged the datasheet and the outputs are actually inputs :dodgy: :scratch: In Holland they say "beetje dom" ...

I built this circuit yesterday and of course I found out immediately. The correct chip should be the 74HC4040. I already rewired the circuit and will get the chip in a few days

I will than repost the circuit for a WORKING one :nod:

stay tuned ! 🙂
 
#10
Further to the missing samples:

I agree, that you will miss samples, or may be we should say, there is a kind of shift as in the samples.

The big question is, and so far there is no scientific proof, can we hear that? I don't know, may be we can, but for sure the effect of a very stable, local clock is doing more for the audible sound, so it might be covered by the better experience you have with this trick.

And as said, I have been doing listening tests between the one and the other and I preferred the Local Clocking.

I agree with you immediately, that if you could link your CD, this would be even much better !!!

Good idea actually and I already start thinking on how to implement this in my set..... thanks for the TIP !! :nod:

Best wishes to Russia !

Doede
 
#12
Marlowe said:
Hello everybody,

Thank Peter Daniel, jean-paul, Elso Kwak, and other guys. I built a simple DAC with CS8412 and TDA1543 on last week.
However I think the jitter of CS8412 is not very low, so I want to do something to decrease it. I have two ideas currently:
1) adding a reclock circuit between CS8412 and TDA1543 or
2) replacing CS8412 by lower jitter digital receiver as AD1892.

What is the choice more worth to try?

Thanks.
Click to expand...

Hi,

I do not yet have good experiences with the AD1892. I'd suggest

- Build or buy a secondary PLL with VCXO that has low jitter
- Use a master clock at the DAC side and feed that back to the drive

regards
 
#13
Hi.
The most global decision of this problem consists in refusal from SPDIF. Three wires to connect from the decoder of CD-drive to the DAC, and one wire to connect the main clock from the built-in DAC generator. Also it is not required D.I.R.
There is necessary to do reclocking LRCK (and may be DATA & Bitclock) synchronous with MCLK, before it will be transferred on DAC IC.

I think, in a case PLL+VCXO jitter will be more, than in case of good XO. VÑXO+PLL will have low-frequency jitter always.

Regards

PS
Someone, who will do it, and if they have nothing against digital filters, I recommend to try AD1896 in a synchronous mode, with 4x oversamplinhg (ad1896 -> shift registers for parallel format transmission ->trigger for reclock).
 
#14
Õàëÿâùèê said:
Hi.
The most global decision of this problem consists in refusal from SPDIF. Three wires to connect from the decoder of CD-drive to the DAC, and one wire to connect the main clock from the built-in DAC generator. Also it is not required D.I.R.
There is necessary to do reclocking LRCK (and may be DATA & Bitclock) synchronous with MCLK, before it will be transferred on DAC IC.

I think, in a case PLL+VCXO jitter will be more, than in case of good XO. VÑXO+PLL will have low-frequency jitter always.
Click to expand...


Hi

Removing SPDIF is OK, if you want to go ahead with the 3 wire interface. The downside is that the format is not accepted by most DACs 🙂

That is why we kept SPDIF, and designed a proper PLL circuit, with 3rd order lowpass, dominant pole around 1 Hz.....

best regards
 
#15
Hi!

That is why we kept SPDIF, and designed a proper PLL circuit, with 3rd order lowpass, dominant pole around 1 Hz.....
Click to expand...

It is much easier to make XO with low phase noise, than VCO. And that level of the jitter, which can be received with XO, in a case VCO is not achievable.

Dominant pole around 1 Hz..... It is required additional RAM FIFO buffer.

On what VCO you will advise to pay attention?

I think, what use I2S certainly extreme method :smash: , but it is most simple and gives perfect result, and if we have started talking about a separate wire of synchronization, why not to decide this problem at once cardinally?




Regards
 
#18
Õàëÿâùèê said:
Hi!

It is much easier to make XO with low phase noise, than VCO. And that level of the jitter, which can be received with XO, in a case VCO is not achievable.

Dominant pole around 1 Hz..... It is required additional RAM FIFO buffer.

On what VCO you will advise to pay attention?

I think, what use I2S certainly extreme method :smash: , but it is most simple and gives perfect result, and if we have started talking about a separate wire of synchronization, why not to decide this problem at once cardinally?
Regards
Click to expand...

Hi,

Let me clarify. A VCXO can be made as low noise as an XO, assumed that the VCXO runs with the control pin fully decoupled. The additional noise at the output of a VCXO is due the control voltage (= output of lowpass of phase comperator, when used in a loop.

The resulting phase noise the depends on

- The incomming noise
- The corner frequency

1 Hz in our design is made in analogue way, with a digital filter that has 2 clock domains, and hence acts as (a very small) buffer.

Please look at our design if you are interested. The measured jitter of a free running VCXO is about 3 ps, within the loop of our DAC, driven with a decent CD drive, it is about 8 ps (both rms, 3 sigma).

My personal preference is not to use SPDIF at all, but it is a standard yet so.....

all the best
 
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