Hi,
I have read somewhere that performance of cs8412 could be improved if one put's external clock to it.
Could an external clock be put on pin 19 (MCK)? Should it's frequency be 256*fs (fs=44.1kHz)?
thanks in advance and best regards
daniel
I have read somewhere that performance of cs8412 could be improved if one put's external clock to it.
Could an external clock be put on pin 19 (MCK)? Should it's frequency be 256*fs (fs=44.1kHz)?
thanks in advance and best regards
daniel
MCK is output of an master clock. It can't be input.... Sorry about my previous stupid q.
Still, I would like to know how and would it be possible to provide better clock for the cs8412 than his internal clock?
If not, is the only thing one can do, to play with SCK?
regards
daniel
The CS8412 is a receiver; its recovers a clock from the incoming AES/SPDIF stream and spits it out... if you somehow could feed it with a clock, then the clock would have to be perfectly synchronized with the SPDIF stream.
Your options are... (in order if increasing complexity)
- improve the PLL layout of the CS8412. If there's a big 600V, inch-long exotic polypropylene capacitor on the board which is used for the loop filter, then kick whoever put it there in the face, and replace it with a proper filter built with 0603 NPO/X5R surface mount parts.
- insert a slow PLL that cleans up the clock output of the CS8412.
- insert a SRC chip to resample incoming data to a decent internal clock, while rejecting almost all of the incoming clock jitter.
- create a MCLK (not SCLK/BCK) signal internally that feeds the MCLK lines of the stuff inside your DAC; disconnect the clock output from the CS8412. Then somehow get that MCLK signal over to your CD player so that it produces data at exactly the correct rate.
Your options are... (in order if increasing complexity)
- improve the PLL layout of the CS8412. If there's a big 600V, inch-long exotic polypropylene capacitor on the board which is used for the loop filter, then kick whoever put it there in the face, and replace it with a proper filter built with 0603 NPO/X5R surface mount parts.
- insert a slow PLL that cleans up the clock output of the CS8412.
- insert a SRC chip to resample incoming data to a decent internal clock, while rejecting almost all of the incoming clock jitter.
- create a MCLK (not SCLK/BCK) signal internally that feeds the MCLK lines of the stuff inside your DAC; disconnect the clock output from the CS8412. Then somehow get that MCLK signal over to your CD player so that it produces data at exactly the correct rate.
hi, gmarsh
a) i have multilayer smd cap in my filter loop (cap and res in series and paralleled with a small cap- like in nonoz II I belive)
b) inserting a slow PLL would be on SCK output pin I guess?
c) inserting SRC chip - You meen something like using RS232 signal receiver ua9637 or similar and throwing it into some nand gates (like 7400) and then in CS8412 (do You have any chips in mind instead of ua9637)
d) to complex
best regards
daniel
a) i have multilayer smd cap in my filter loop (cap and res in series and paralleled with a small cap- like in nonoz II I belive)
b) inserting a slow PLL would be on SCK output pin I guess?
c) inserting SRC chip - You meen something like using RS232 signal receiver ua9637 or similar and throwing it into some nand gates (like 7400) and then in CS8412 (do You have any chips in mind instead of ua9637)
d) to complex
best regards
daniel
b) slow pll means feeding the RMCK signal into a 1:1 PLL, with a low-jitter oscillator (eg a VCXO) and a low loop bandwidth.sparkle said:
c) SRC chip means something like an Analog Devices AD189x or a TI/BB SRC419x chip.
correction from earlier, (c) is less difficult than (b)
Thanks - I think I will concentrate on C) for now- digital is not my thing so I will be free to ask q's when they come
thanks for replies
daniel
thanks for replies
daniel
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