Cs4270 <-> Fpga
I am currently controlling a CS4270 with an FPGA (verilog) in Slave mode. I have studied the datasheets extensively. I am sending the device 24 bit two's complement stereo audio.
I am observing a waveform on my oscilloscope that only partially corresponds to the data I am sending it.
I am sending it 24bit data (in each stereo sample): data[7:0],zeros[15:0] where data[7] is the MSB of an 8bit number, data, that I am incrementing and allowing to overflow. I would expect that I would see something like the following on my oscilloscope:
/| /| /
/ | / | /
| / | /
|/ |/
But what I am getting is:
\ |\ |
\ | \ |
| | | |
| / | / <------ This part, the tip is curvy
If this is inverted then it is close but is not quite what I would expect, especially the part where it drops low quick and goes curvy.
I have checked all my verilog simulations and waveforms. Everything is perfect. I am happy to post my vcd files, verilog source etc. if anyone is interested. All of my timings are well within the specs for the CS4270.
Does anyone have any ideas as to what is going on?
I am currently controlling a CS4270 with an FPGA (verilog) in Slave mode. I have studied the datasheets extensively. I am sending the device 24 bit two's complement stereo audio.
I am observing a waveform on my oscilloscope that only partially corresponds to the data I am sending it.
I am sending it 24bit data (in each stereo sample): data[7:0],zeros[15:0] where data[7] is the MSB of an 8bit number, data, that I am incrementing and allowing to overflow. I would expect that I would see something like the following on my oscilloscope:
/| /| /
/ | / | /
| / | /
|/ |/
But what I am getting is:
\ |\ |
\ | \ |
| | | |
| / | / <------ This part, the tip is curvy
If this is inverted then it is close but is not quite what I would expect, especially the part where it drops low quick and goes curvy.
I have checked all my verilog simulations and waveforms. Everything is perfect. I am happy to post my vcd files, verilog source etc. if anyone is interested. All of my timings are well within the specs for the CS4270.
Does anyone have any ideas as to what is going on?
Sorry its been a few days, I've been away from internet access. I just got back and the problem I had was that the VQ and Filt+ were connected and they are outputs. It seems like I would have seen that when I designed the prototype board, but I didn't. I thought they needed voltage, until I read the specs closer. Next time my prototype board will just have more jumpers and headers, rather than hard wired connections.
I have now gotten it to work and the output is just as in that first rough sketch (in other words it gives the the correct output). Now I'm gonna put an input port on the FPGA to send it audio from an embedded board. You can develop stuff with FPGA's for next to nothing using Xilinx' free design compiler/mapper/router and Gnu licensed Ikarus verilog and gtkwave. Why use an FPGA? Timing of the waveforms is extremely predictable and simulatable (is that a word?), where with an Atmega AVR, PIC, ARM, etc you gotta deal with processor overhead and cycle timing calculations for each instruction/branch. That would be a royal pain in the butt and even worse if I needed to change something! In other words its a bit like walking a tightrope while carrying a beverage tray vs walking on pavement.
Why am I doing this? I wanted a cheap, high quality audio output for my embedded systems, and I also just wanted to do it. I think I can crunch all the logic down to a cheap CPLD, and this CS4270 chip so that the total cost is < $5
Contact me if you're interested in this project.
-Brian
I have now gotten it to work and the output is just as in that first rough sketch (in other words it gives the the correct output). Now I'm gonna put an input port on the FPGA to send it audio from an embedded board. You can develop stuff with FPGA's for next to nothing using Xilinx' free design compiler/mapper/router and Gnu licensed Ikarus verilog and gtkwave. Why use an FPGA? Timing of the waveforms is extremely predictable and simulatable (is that a word?), where with an Atmega AVR, PIC, ARM, etc you gotta deal with processor overhead and cycle timing calculations for each instruction/branch. That would be a royal pain in the butt and even worse if I needed to change something! In other words its a bit like walking a tightrope while carrying a beverage tray vs walking on pavement.
Why am I doing this? I wanted a cheap, high quality audio output for my embedded systems, and I also just wanted to do it. I think I can crunch all the logic down to a cheap CPLD, and this CS4270 chip so that the total cost is < $5
Contact me if you're interested in this project.
-Brian
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