Connecting two I2S sources to one DAC - How to switch, what to do with the MCK lines?

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Groundloops

Groundloops

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Joined 2004
#1
Having two I2S sources, namely Amanero asynchronous USB-to-I2S and S/PDIF transceiver WM8805, and a dual differential WM8471 DAC.

Regarding the SCK, SD and WS lines swichting can be as simple as this:

185948d1283211592-simple-i2s-multiplexer-multiplexer2.jpg


But what to do with the MCK (clock) lines? The Amanero has a 24.576 MHz clock, the WM8805 derives it's frequencies from a 12.00 MHz clock. Do I have to switch both the MCK lines as well? If so, will a MUX suffice?

Shed some light on me please ... :worship:
 
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#3
WM8805 has: "Configurable clock distribution with selectable output MCLK rate of 512fs, 256fs, 128fs and 64fs."... so it's MCLK output should definitely not be 12MHz. Do you gave a schematics or at least description of your WM8805 transceiver?

Check out OTTO-II 2:1 Digital Switch Module from TPA
Use it's 0.1" (2.5mm) pin headers not the terminal blocks.

Zsolt
 
#5
The diagram you shown is for external clock input. I just ran through WM8805 datasheet but I think it uses this input (10-27MHz) to generate through its internal PLL a correct MCLK - so don't think you should care much about it.

What you should care is the Digital audio interface figure from eval board datasheet: see attached - you have there all I2S signals + MCLK

Don't know what Otto II actually uses - email the designer. Some sort of Quad 2-Input Multiplexer, e.g. 74VHC157 or similar.

Zsolt
 

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#6
The WM8805 uses 10-27 MHz clock in software mode only, if I understood the datasheet right. In hardware mode the clock must be 12 Mhz.

I'm beginning to think about a possible alternative to the WM8805 ...

I don't feel comfortable with the idea to have the MCK line running through a mutliplexer - propagation delay may (will?) add jitter.

Again, thank you!
 
#7
Groundloops said:
The WM8805 uses 10-27 MHz clock in software mode only, if I understood the datasheet right. In hardware mode the clock must be 12 Mhz.
Click to expand...
This clock's frequency has nothing to do with output MCLK frequency. Forget about this 12MHz clock. MCLK frequency is generated through WM8805's internal PLL to be relative to the input stream frequency.
If you are using it in hardware mode - WM8805 pg30:
"FREQMODE control is fully automatic to ensure that the MCLK output is maintained at 256fs relative
to the S/PDIF received sample rate.
In hardware mode, the OSCCLK must be 12MHz and hence the external crystal (or applied XIN clock) must be 12MHz. No other OSCCLK frequencies are supported in hardware mode"

Groundloops said:
I'm beginning to think about a possible alternative to the WM8805 ...
Click to expand...
Don't have to. Simply use H8 output - you have there all I2S lines (incl. MCLK) - and forget about the 12MHz clock.

Groundloops said:
I don't feel comfortable with the idea to have the MCK line running through a mutliplexer - propagation delay may (will?) add jitter.
Click to expand...
No, propagation delay is not same with jitter. Somewhere on the forum were discussing (was also a table) about jitter added by different flip-flops... don't remember exact numbers but it was irrelevant (<1ps if I remember well). Ask Otto II designer, he might know - also he might recommend you a good multiplexer (maybe VHC or AHC series)
You could also use impedance matched RF relays, but you must design a proper PCB for it otherwise is meaningless.

Zsolt
 
#8
Thank you even more, Zsolt! :worship:

Slowly, very slowly I'm getting an idea ...
MCLK output is maintained at 256fs relative to the S/PDIF received sample rate.
Click to expand...

So I understand: When SPDIF input sample rate is 44.1 kHz, then MCLK output is 11.2896 MHz, 96 kHz in is 24.576 MHZ out and so on up to 192 kHz/49.152 MHz.
So the 12.00 MHz clock on the WM8805 is not a master clock in common sense as it works in indivisible relation to the sample rate of the SPDIF input.

It seems I'm somehow mixing up different things and/or I lack the basic understanding of the master clock concept in general ... 🙄

Anyway: In what I want to achieve I neither can use the Amanero's 24.576 MHz nor the WM8805's 12.00 MHz clock as a master clock:

fstable.jpg

fstable-2.jpg


I conclude that I need an ASRC. Or is there any voltage-out DAC that takes any sample rate without an ARSC?
 
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#9
Groundloops said:
So I understand: When SPDIF input sample rate is 44.1 kHz, then MCLK output is 11.2896 MHz, 96 kHz in is 24.576 MHZ out and so on up to 192 kHz/49.152 MHz.
So the 12.00 MHz clock on the WM8805 is not a master clock in common sense as it works in indivisible relation to the sample rate of the SPDIF input.
Click to expand...
The 12MHz is the master (in a way) as it is used by the PLL to generate the desired MCLK.
Check the PLL in datasheet if you want to know more how MCLK is generated.

Groundloops said:
Anyway: In what I want to achieve I neither can use the Amanero's 24.576 MHz nor the WM8805's 12.00 MHz clock as a master clock:

fstable.jpg

fstable-2.jpg
Click to expand...

Amanero has "fixed" MCLK of 22.5792MHz/24.576MHz so according to the sample rates image WM8741 should work from 44.1Khz to 192KHz fine.

WM8805 seems to have fixed MCLK (fsx256) in hardware mode so it will work from 44.1KHz to 96KHz. For 176.4/192KHz you need (probably) software mode to have MCLK fsx128.

I think I cannot help more. Connect both to your DAC and see how it works. Use an Otto II or similar to switch between I2S sources.

Zsolt
 
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