Hello,
I am attempting to mod a Yamaha MU80 to produce S/PDIF digital output. I have previously modded a Yamaha MU100 by using an AK4103A DIT. This was fairly simple; the digital audio stream going to the DAC (NEC UPD63200) on the MU100 is a 18-bit right-aligned PCM stream with a single data line, which the ak4103a supports, and I didn’t need any extra circuitry besides a few capacitors.
Below is a screenshot from a capture that I did of the MU100's digital audio stream:
I'd like to also add a SPDIF mod to the MU80, but the digital audio stream going to the DAC is a bit different:
Everything else is the same, but the data is split into separate left and right data streams and are sent simultaneously.
I know of no DIT that can take in left/right channels on separate lines, so, I figured what I would do is use a shift register to shift the right channel 32-bits, then multiplex them using something like the 74fst3257. I was looking at the CD4517B for the shift register; This does 64 bits and has a 32-bit output, and it seems to be rated to do at minimum 3Mhz at +5V (unlike the HEF4517 or the MC14557), but I am concerned about the propagation delay:
In particular, the variance between the typical and maximum at +5v concerns me; the difference is greater than the bit clock pulse width. Would this still be an appropriate choice for this, or would I be better served with another IC(s)?
I am attempting to mod a Yamaha MU80 to produce S/PDIF digital output. I have previously modded a Yamaha MU100 by using an AK4103A DIT. This was fairly simple; the digital audio stream going to the DAC (NEC UPD63200) on the MU100 is a 18-bit right-aligned PCM stream with a single data line, which the ak4103a supports, and I didn’t need any extra circuitry besides a few capacitors.
Below is a screenshot from a capture that I did of the MU100's digital audio stream:
- 18-bit right aligned PCM stream
- MSB first
- Sample rate is 44100Hz
- bit clock is 64fs (64*44.1KHz = ~2.822MHz)
- word clock is 2*44.1KHz
- 32 bit cycles per word transition
- Word high is left channel, word low is right channel
I'd like to also add a SPDIF mod to the MU80, but the digital audio stream going to the DAC is a bit different:
Everything else is the same, but the data is split into separate left and right data streams and are sent simultaneously.
I know of no DIT that can take in left/right channels on separate lines, so, I figured what I would do is use a shift register to shift the right channel 32-bits, then multiplex them using something like the 74fst3257. I was looking at the CD4517B for the shift register; This does 64 bits and has a 32-bit output, and it seems to be rated to do at minimum 3Mhz at +5V (unlike the HEF4517 or the MC14557), but I am concerned about the propagation delay:
In particular, the variance between the typical and maximum at +5v concerns me; the difference is greater than the bit clock pulse width. Would this still be an appropriate choice for this, or would I be better served with another IC(s)?
Maybe have a look at 74AHCT164? Writing the channels onto one line can be done with fast logic gates...
That definitely would have significantly less propagation delay; max of 12.5ns at normal operating temperatures, so four of them in a series would only have a max of 50ns of propagation delay.
I was about to say that could work, when I realized another difference between the mu80 and the mu100 that could give me serious problems:
Here is the typical pulse width of the data line before the clock falling edge on the MU100; it transitions up and down between 80-100ns before the falling edge.
Here's the pulse width before the clock falling edge for the MU80, most of them are short enough that my logic analyzer can't capture it @ 50Ms/s. The longest I see is 20ns, so about 0-20ns
so not only would I have to adjust the clock about half a pulse width so that it isn't seriously affected by the propagation delay, the added impedance of the wires going to the DIT board and the DIT board itself could seriously interfere with the operation of the DAC. Can anyone offer me advice on how to tackle either of those? The impedance problem might be solved via terminating resistors, but I’m not sure how to dial those values in.
I was about to say that could work, when I realized another difference between the mu80 and the mu100 that could give me serious problems:
Here is the typical pulse width of the data line before the clock falling edge on the MU100; it transitions up and down between 80-100ns before the falling edge.
Here's the pulse width before the clock falling edge for the MU80, most of them are short enough that my logic analyzer can't capture it @ 50Ms/s. The longest I see is 20ns, so about 0-20ns
so not only would I have to adjust the clock about half a pulse width so that it isn't seriously affected by the propagation delay, the added impedance of the wires going to the DIT board and the DIT board itself could seriously interfere with the operation of the DAC. Can anyone offer me advice on how to tackle either of those? The impedance problem might be solved via terminating resistors, but I’m not sure how to dial those values in.
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Maybe adjust alignment by reclocking with fast flip flops? Impedance matching with series resistors is what we see in many schematics of commercial products.
What chip handles the signal going to the DAC chips of the MU80? Maybe you can take the signal for the AK4103 somewhere upstream?
What chip handles the signal going to the DAC chips of the MU80? Maybe you can take the signal for the AK4103 somewhere upstream?
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I went and looked at the DAC (UPD63200) datasheet again; it turns out that I had misread it (which was easy to do, since it’s very poorly translated from Japanese), and it’s the RISING edge that’s the clock state, not the falling. This means that this scheme with 4x74AHCT164s in series is fine and the propagation delay won’t affect it at all; I have about 120ns of wiggle room because the data transitions on the clock falling edge. Thanks for the advice, jpk73!
The MEG (Multi-Effects Generator, synth ASIC) outputs those lines straight to the DAC (it also outputs the HCLK that I use as the 128fs MCLK, and the RESET (CS) line). I am likely going to have to solder the lines to these terminating resistors next to the MEG anyway, as there are no real headers or vias to solder to. On the MU100, these are all output straight to an unused header that goes to an external DAC board on the Rack mounted version (MU100R), which made this a cinch.
I went ahead and made the schematics for the board. I decided to use a DIT that was easier to find than the AK4103A so that I could just have this SMT assembled by JLCPCB: the CS8406A. It only supports 16-bit and 24-bit right-aligned PCM when in stand-alone mode, so I decided to use another 74AHCT164 to shift the word clock right 6 cycles to convert the 18-bit words to 24-bit words. I am using a 74FST3257 multiplexer that has minimal propagation delay to mux the LSI and shifted RSI together, with the shifted word clock as the selector.
The major concern that I have about this design is that I'm using the bit clock in 6 separate places; do you think it would be wise to put a clock buffer on here?
The MEG (Multi-Effects Generator, synth ASIC) outputs those lines straight to the DAC (it also outputs the HCLK that I use as the 128fs MCLK, and the RESET (CS) line). I am likely going to have to solder the lines to these terminating resistors next to the MEG anyway, as there are no real headers or vias to solder to. On the MU100, these are all output straight to an unused header that goes to an external DAC board on the Rack mounted version (MU100R), which made this a cinch.
I went ahead and made the schematics for the board. I decided to use a DIT that was easier to find than the AK4103A so that I could just have this SMT assembled by JLCPCB: the CS8406A. It only supports 16-bit and 24-bit right-aligned PCM when in stand-alone mode, so I decided to use another 74AHCT164 to shift the word clock right 6 cycles to convert the 18-bit words to 24-bit words. I am using a 74FST3257 multiplexer that has minimal propagation delay to mux the LSI and shifted RSI together, with the shifted word clock as the selector.
The major concern that I have about this design is that I'm using the bit clock in 6 separate places; do you think it would be wise to put a clock buffer on here?
I am no expert in clock distribution, but in my logic circuits I could feed multiple ICs from one signal if series resistors (22R-47R) were placed near the source. And also check the datasheet of the source IC to see if it can drive the inputs of the receiving ICs...
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