Clock transmission

Having done some reading about transmission lines, I'm curious as to how the experts here address clock transmission and distribution problems. (no family secrets required, just some insight ^_^)

I've seen Harry's ganged-inverter driver, but I wonder if this addresses the distribution issue, as the clock would still have to drive N inverters with nonzero pin capacitance to drive N transmission lines. Is this a nonissue if the clock-to-drivers block is a lumped system?

What about Elso's JFET driver? I would imagine an SMT transistor would be necessary to keep parasistic capacitance to a reasonable figure.

I ask this question mainly because most of the designs (commercial and otherwise) I've seen appear to give absolutely no thought to driver loading and transmission line termination. Some figures I've cooked up show that even with a few drops and SMT components the capacitive loading is so high that ringing contributes a huge amount of delay, even with Tr=4ns and short (<2 in) traces.

I'm not sure whether or not this is really significant though...if the delay is nondeterministic, then I would see it contributing to jitter, but if it simply causes skew then it may not be an issue for audio applications, provided the delays to each component are balanced. I would think that the radiated EMI caused by all of these reflections would be very undesirable though regardless of the effect on the signal integrity.

I'm working through Dr. Johnson's "High Speed Digital Design", but at the moment it is seeming like the more I know the more unsolvable the problems become!

Perhaps I should note that here it is stated that with trace lengths < 3in, ringing of unterminated lines is "acceptable" in the test case (Tr=3ns, Zo=75, CL<=50pF).
Clock & SPDIF Transmission

Hi, Tiroth,
The schematic I used was borrowed from Horrowitz-the Art of Electronics- and a Analog Devices paper.
I just switched the 2N4401 for a FET.
The idea is to properly terminate a 75 coax cable at <B>both</B> ends i.e. a 75 Ohm resistor in series with the core at the sending end and a 75 Ohm resistor from the core to ground at the receiving end to omit reflections at both ends of the cable.
The FET is however not a perfect follower, has a few hundred Ohms outputresistance (again Horrowitz) making the 75 Ohm resistor from the source of the FET to the core a bit foolish. Jocko reminded me of this in a private email.
This led me to include a very fast video buffer OPA603 which has very low output impedance with feedback applied. It is a current feedback amplifier and the datasheet recommends a 2k8 feedback resistor. I first tried the AD811 and AD817. I am using a 1m (4feet) cable from the CDP to DAC. Waveforms look perfect at the receiving end.
When using the interface with the OPA603 omitted I see a slight glith on the square wave just as in the Analog Devices paper [Section2 High Speed Opamp Application Walt Kestner, Walt Jung] using 13 meters of sheep , non double shielded coax. With the opamp waveforms look perfect; even with the long cable and sound is OK too.
The DCoffset starting from the source of the FET places the square wave in the common mode range of the comparator.

;) ;)
Interface schematic:
Perhaps I should clarify; I was asking a general question about transmission and distribution, i.e. from a clock source to n destinations, with trace lengths possibly only inches long. I think your input is valuable, but it doesn't answer the question as to whether or not a clock source (e.g. HC or ACT CMOS) is capable of driving n copies of your circuit.
Thanks Jocko. I may need to use a couple of AC components in my divider because of my timing budget...should I buffer this with an HC inverter?

As far as speeds go my specific application is the divider I asked about previously; 49.152MHz clock driving a pair of syncronous counters to get 1/2, 1/4, and 1/256. I need to do some more careful timing analysis, but I think I may need AC timing for both the counters and their latch.

I'm a bit concerned about series termination, as my single-driver model could have a fan-out of 8. With SMT components, Cl=40pF, is this too heavy a load? Would it be better to use multiple drivers?
What about the VHC(T) series (Fairchild, OnSemi and others). It can accept clocks up to 180 MHz. Has anyone tested it ?

Concerning 74F(AST) series, look at Fairchild products that have a built in termination resistor (if memory serves, not all the chips in the series have it, but it's mentionned when implemented). Moreover, Fairchild has some well done technical papers/application notes on designing with this series, and particularly on the termination/transmission problems... (I don't have the reference handy, but tell me if you need it)
Jocko--well, that is less disheartening than your reaction to AC logic. ;) Does a pair of 74F163s latched by a 74HC574 meet your criteria for a "clean" clock?

ftorres--I looked at VHC(T) but had a hard time finding a diverse set of chips in that family. I don't know if you've had similar results.

As far as the white papers, were you referring to Fairchild AN-661 ("FAST Design Considerations")? If not, I'd certainly be interested if it isn't too much trouble for you to dig it up.

Thank you both for the input.

Yes, I quickly checked my files, and AN661 is the main paper I had in mind. But AN-754 ( ) and MS-520 ( ) are worth reading, and also are (but less related) AN610 ( ), MS529 ( ) and ( ).

I also had problems finding the VHC devices. Fairchild makes a VHC163 (but not OnSemi), and does not offer samples :(, but I couldn't find some in France. Farnell offers some, but not this one :(. You should be luckier in the US. OnSemi offers samples (up to 10 at a time) for the VHC574, and they are pretty fast with the delivery. But it only comes in the SMT flavour (which I tend to prefer for high speed designs, but it's a pain to prototype with such devices). If my memory's still OK, Digikey offers the Toshiba's VHC Series.

Hope this helps
I'm just fiddling with my limited knowledge, but is it right to speak of transmission lines when considering a 50MHz signal (yes, the 9th harmonic is at 450MHz) with relatively short PCB traces ?
If the answer is yes, the PCB should be designed to provide microstrip (or other transverse geometries) lines with the right Zc to critical signals. My school days are far away now, but it seems to me that a 50R Zc line would be quite wide on FR4 material, and this width would not be compatible with the tiny pitch of today's SMT devices.
Narrowing the traces will result in an increased Zc, and thus in an increased sensivity to external perturbations. Where did I go wrong ?