clock regeneration article on planetanalog.com

[mlloyd1]

Worry about clocks,jitter, etc.?, Maybe some interesting reading here
"Programmable clock regeneration techniques get signals through extreme conditions"

mlloyd1

 

[andrei]

Interesting. Using one of these "failsafe" clock buffers (CY23FS04/CY23FS08) will significantly clean up DIR-recovered clock at very small expense in money/board space. Very interesting indeed...

 

[Elso Kwak]

Clock Distribution Article

Hi Michael,
Interesting article, but not for the novice.
Andrei, I did not find the CY23FS06 and CY23FS08 in the article but here:
http://www.electronicstalk.com/news/cyp/cyp199.html
I will dig into it.😉

 

[andrei]

The CY23FS04/CY23FS08 datasheets are at the Cypress website. Take a special look at the application note "Using Failsafe CY23FS08 as a Clock Jitter Reducton Device". The only external component required is a standard crystal (which is cheap and easily available in digital audio clock frequencies, unlike VCXO modules). Plus you get 3/7 buffered clock outputs for free, which you probably need anyway unless you are using monolythic digital filter/DAC chip.

To repeat myself, very interesting...