CD master clock

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#21
The simple fact is that the PCM1732 DAC (at least in SRC upsample mode) is operated from the 24MHz clock irrespective of the jitter attenuation abilities of the SRC.

No matter how good the transport section clock is, IT CAN NEVER BE BETTER then the DAC’s 24MHz Master Clock, as the DAC’s Master clock is the critical “Heart Beat” of the Digital to Audio conversation. The Jitter performance (Phase Noise) on the DAC’s master clock will take precedence over any proceeding "perfect" clock – this is an undisputable fact.

Therefore, with this essential fact in mind, the DAC’s master clock (24MHz) must be improved to a point where it is not the limiting factor. We could discuss until the cows come home the virtues of SRC jitter attenuation and re-latching the I2S data, but the significance of the quality of the Master Clock performance operating the DAC Audio conversion is an undeniable reality.
 
#24
JohnW said:
The simple fact is that the PCM1732 DAC (at least in SRC upsample mode) is operated from the 24MHz clock irrespective of the jitter attenuation abilities of the SRC.

No matter how good the transport section clock is, IT CAN NEVER BE BETTER then the DAC’s 24MHz Master Clock, as the DAC’s Master clock is the critical “Heart Beat” of the Digital to Audio conversation. The Jitter performance (Phase Noise) on the DAC’s master clock will take precedence over any proceeding "perfect" clock – this is an undisputable fact.

Therefore, with this essential fact in mind, the DAC’s master clock (24MHz) must be improved to a point where it is not the limiting factor. We could discuss until the cows come home the virtues of SRC jitter attenuation and re-latching the I2S data, but the significance of the quality of the Master Clock performance operating the DAC Audio conversion is an undeniable reality.
Click to expand...

Hi

You cannot generalise such a statement

Much depends on the properties of the DAC chip itself, how it deals with incoming jitter. On chip crosstalk very much affects conversion proces

Once you know that, you know how sensitivity is of drive ves DAC clock quality

cheers
 
#26
Gentlemen,

just for your information. I replaced both clocks. It made a big difference and my friend was very satisfied with the sound. Before the change of clocks it wasn´t possible to hear any difference between standard and 24/96 mode, after the mods the difference was obvious.
Sound in generall improved in the usual way and the player was now "listenable" also for longer hearing sessions🙂
I didn´t change any other part (power supply, opamps).


william
 
#28
Any hints on where I can find a suitable clock-board for this CDP, preferably one that isn´t too hard to install?

found LC audio clocks , but £400 for two clocks is a bit steep

are there any other "must have" upgrades that I should consider before gutting my CDP?.

Regards
 
#30
Hi
I have a problem to solve.
I would like to put a kwak clock on my SAA7327 jolida JD100 controller.

The problem is that there are a clock-in and a clock-out pin on the SAA7327. I have only one output on my kwak clock.
I've looked at the SAA7327 data-sheet and it seems that this ic only work with crystals.

Is someone would have any clue ?
 
#32
arnaudb said:
Hi
I have a problem to solve.
I would like to put a kwak clock on my SAA7327 jolida JD100 controller.

The problem is that there are a clock-in and a clock-out pin on the SAA7327. I have only one output on my kwak clock.
I've looked at the SAA7327 data-sheet and it seems that this ic only work with crystals.

Is someone would have any clue ?
Click to expand...


Hi,

(Kwak) clock output normally goes to chip input (pin 16). Connect clock ground as close as possible to the SAA chip (preferably pin 14).

Please note that this chip runs on 3.3V, so the clock output voltage shouldn't be higher than that.

enjoy
 
#33
JohnW said:
The simple fact is that the PCM1732 DAC (at least in SRC upsample mode) is operated from the 24MHz clock irrespective of the jitter attenuation abilities of the SRC.

No matter how good the transport section clock is, IT CAN NEVER BE BETTER then the DAC’s 24MHz Master Clock, as the DAC’s Master clock is the critical “Heart Beat” of the Digital to Audio conversation. The Jitter performance (Phase Noise) on the DAC’s master clock will take precedence over any proceeding "perfect" clock – this is an undisputable fact.

Therefore, with this essential fact in mind, the DAC’s master clock (24MHz) must be improved to a point where it is not the limiting factor. We could discuss until the cows come home the virtues of SRC jitter attenuation and re-latching the I2S data, but the significance of the quality of the Master Clock performance operating the DAC Audio conversion is an undeniable reality.
Click to expand...

Both the transport's masterclock and the clock at the DAC are important I learned.
 
#34
KC feeding a 5V chip

Guido Tent said:
Hi,
(Kwak) clock output normally goes to chip input (pin 16). Connect clock ground as close as possible to the SAA chip (preferably pin 14).
Please note that this chip runs on 3.3V, so the clock output voltage shouldn't be higher than that.
enjoy
Click to expand...

You can run the KC at +/- 3.3V but you must be aware that the comparator AD8561 does not put out 5V but typically 3.5V for a logic "high" voltage. So you need only a slight attenuation, if any, of the clocksignal compared with feeding a 5V chip.
😎
 
#35
You could have the most perfect clock on the transport section (primary side of ASRC), however if the clock operating the secondary side of an ASRC which also operates the DAC is poorer then the primary side, the benefit of the better transport clock is significantly degraded.

The phase noise performance of an ASRC can never be better then the Secondary side Master clock. Put your best clock on the secondary side – then improve the primary side clock.

I find it frustrating, the some people cannot understand that in an ASRC system the DAC is ultimately Clock by the secondary side clock and the SRC will offer no attenuation to this clocks phase noise.

Notice I used the word “attenuation” – meaning the level of phase noise on the primary side is still important – but if you have a choice, add your second best clock here - its Phase noise will be ATTENUATED by the ASRC – so long as the ASRC secondary side clock is of LOWER PHASE NOISE.

In a typical system, the primary side clock (the transport clock) will be implemented as a part of the CD servo decoder i.e. form part of the crystal oscillator “block” on the CD decoder IC. Due to the very poor short term phase noise performance of these integral oscillator circuits – improving this clock will bring large benefits.

As most modern DAC’s and ASRC don’t have onboard crystal circuits (for good reason), they necessitate the use of a “off chip” clock circuit, and thus the secondary side clock will normally be of inherently higher quality.

So once again, best clock on ASRC Secondary side, second best clock on primary side of ASRC where it will gain the benefit of the SRC jitter attenuation.

Elso my hat off to you if that’s your Wife / Girlfriend in your avatar!

Regards,

John
 
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