A 9mA jFET with 10r in the Source will run @ 6 to 7mA not @ 10mA.
Even a V grade would probably not manage 10mA with 10r of degeneration.
Even a V grade would probably not manage 10mA with 10r of degeneration.
Just take a look at the original schematic, you will clearly see 100R trimmer. Also when you look at the original schematic - Hiraga specified the highest hfe and Idss components for all transistors. This is why the selection of suitable modern substitutes is such a pain in the *** to get right.
Shoog
Shoog
I changed it to those lower values to see if it would pass more current. It wouldn't move off 0.4mA which indicated a fault with the spice model. when this was corrected it started conducting at about 7mA with those values - but it meant that the load resistor needed to be to small. After various tweaks I got it working correctly with the 100R bias pot and an adequate load resistor whilst maintaining the output bias current at a sensible 840mA.
Shoog
Shoog
Dale was very kind and rebuilt my simulation for me, whatever it was was probably due to jfet orientation rather than the model itself. These jfets are supposed to be bidirectional - but I don't think the models reproduce this.
Shoog
Shoog
I will be placing an order for the bits and pieces I need this week so hopefully will be building by the weekend.
Shoog
Shoog
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