Cambridge Discmagic & Dacmagic 2 schematics wanted
Anbody have schematics/service manauls available for these? I've found one page for the dacmagic in an old thread, but I really need the rest as well.
I'm looking at trying to get the dacmagic to generate the 'clock lock' signal to send back to the discmagic (which already has a clock input). Anyone know how feasible this is?
Anbody have schematics/service manauls available for these? I've found one page for the dacmagic in an old thread, but I really need the rest as well.
I'm looking at trying to get the dacmagic to generate the 'clock lock' signal to send back to the discmagic (which already has a clock input). Anyone know how feasible this is?
Hi Mike,
Its worthwhile to improve the "recovered" clock within the DacMagic - the TDA1315 recovered clock phase noise is very poor.
If you want to modified the DacMagic so that ONLY works with the DiscMagic then this is easier then trying to allow the DacMagic to work with other sources once modified due to clock routing / selection.
You will have to add a 256Fs Clock, 11.2896MHz to the DacMagic, and divide by 2 (resulting in a 5.6448MHz clock) and feed this to the DacMagic.
If you find the data sheet for the TDA1315, lift its clock output Pin, and feed the 11.2896MHz Clock to this pad (PCB pad, not IC pin), and also feed the divided by 2 clock (5.6448MHz) to the transport – the DAC and transport will now be ClockLocked.
JohnW
Its worthwhile to improve the "recovered" clock within the DacMagic - the TDA1315 recovered clock phase noise is very poor.
If you want to modified the DacMagic so that ONLY works with the DiscMagic then this is easier then trying to allow the DacMagic to work with other sources once modified due to clock routing / selection.
You will have to add a 256Fs Clock, 11.2896MHz to the DacMagic, and divide by 2 (resulting in a 5.6448MHz clock) and feed this to the DacMagic.
If you find the data sheet for the TDA1315, lift its clock output Pin, and feed the 11.2896MHz Clock to this pad (PCB pad, not IC pin), and also feed the divided by 2 clock (5.6448MHz) to the transport – the DAC and transport will now be ClockLocked.
JohnW
Thanks John, I thought you might have the answer!
I was thinking of using the tent xo-2 or xo-3 clock module as these have an optional /2 clock output. The xo-3 also offers reclocked spdif - would there be any advantage using that in the dac? I assume that even without reclocking latency of sending the clock back and the receiver regenerating it will be negligible, i.e. the data, ws, bck will still be synced closely to the 256fs CLK.
Another couple of questions - my DAC has OPA2132 and OPA132 op amps (in sockets), I assume this was not how it originally left the factory? What does the single op amp chip do, it's not on the page 3 of the schematic that I have.
Also, (briefly) how are the inverted L and R i2s signals generated - is it a feature of the receiver or xextra logic?
I was thinking of using the tent xo-2 or xo-3 clock module as these have an optional /2 clock output. The xo-3 also offers reclocked spdif - would there be any advantage using that in the dac? I assume that even without reclocking latency of sending the clock back and the receiver regenerating it will be negligible, i.e. the data, ws, bck will still be synced closely to the 256fs CLK.
Another couple of questions - my DAC has OPA2132 and OPA132 op amps (in sockets), I assume this was not how it originally left the factory? What does the single op amp chip do, it's not on the page 3 of the schematic that I have.
Also, (briefly) how are the inverted L and R i2s signals generated - is it a feature of the receiver or xextra logic?
Mike,
When you ask about the "single op amp chip" are you referring to the UA9637? it’s near the Digital input BNC connecters - if so its Balanced Line receiver - converts the "500mV" SPDIF signal levels to CMOS / TTL 5V - not part of the analogue circuits.
For sure the OPAMP’s where not fitted in sockets, AD712 where standard fit.
No need to reclock the SPDIF - so XO-2 should be OK.
The L/-L R/-R I2S signals are generated by the Logic chips,
JohnW
When you ask about the "single op amp chip" are you referring to the UA9637? it’s near the Digital input BNC connecters - if so its Balanced Line receiver - converts the "500mV" SPDIF signal levels to CMOS / TTL 5V - not part of the analogue circuits.
For sure the OPAMP’s where not fitted in sockets, AD712 where standard fit.
No need to reclock the SPDIF - so XO-2 should be OK.
The L/-L R/-R I2S signals are generated by the Logic chips,
JohnW
I'm still looking for schematics for these - particularly the clock locking circuit in the discmagic.
When I put a clock signal into the discmgic the clock lock led lights up as expected, but the relay doesn't click over (it's not getting any signal) to change the clock source. I've tried tracing the circuit on the pcb, but can't figure it out.
When I put a clock signal into the discmgic the clock lock led lights up as expected, but the relay doesn't click over (it's not getting any signal) to change the clock source. I've tried tracing the circuit on the pcb, but can't figure it out.
I have start a new thread regarded problems by clock generator adjustment:
http://www.diyaudio.com/forums/digi...t-adjustment-instruction-vr1.html#post2481298
http://www.diyaudio.com/forums/digi...t-adjustment-instruction-vr1.html#post2481298
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.