I have a problem with my AD1853 DAC that I think may be caused by an invalid MCLK frequency, but I'm not certain due to some interesting things in the datasheet. Perhaps someone can assist...
The situation:
192kHz L/R clock
12.288MHz bit clock
24.576MHz master clock
INT4X is low, INT2X is high
However, the ZEROR and ZEROL pins are always low, indicating no data.
Now, Table II on page 8 indicates that 128xFs (24.576MHz here) is a supported MCLK frequency for Fs=192kHz. However, on page 3 it also says that MCLK period must be greater than 54ns (e.g. clock slower than 18MHz), except when using "Master Chip clock auto-divide feature." It also specifies that this period is for 256xFs mode, and doesn't speak to other multiples.
Before I start rerouting clocks, can anyone opine as to whether my MCLK is too high? I would guess that the "divide" feature is only for 512xFs and 768xFs, which means that at 128xFs my clock is too hot. Should I cut MCLK to 64xFs, 12.288MHz? I'm reluctant to do this when Table II clearly states that 128xFs is acceptable, but the behavior of the DAC looks to me like it isn't properly processing the input at all.
Here are all of the stupid mistakes I've thought to check for: I've measured the clocks and the SDATA line on the DAC pins, so I know these signals are being received, and that there is data on the SDATA line. I've triple checked the serial input format, although I would expect to get output even if this were wrong. I've used a reset generator to reset the chip (works fine with the other Analog IC on this board), and the ~RST line is high. Mute is low. Serial control pins are pulled low through 10K resistors. Supplies are nominal and grounds are connected. Oh, and my DIR is locked and outputting valid data.
I'm deeply in the debt of anyone who can offer some ideas. Thanks for looking!
The situation:
192kHz L/R clock
12.288MHz bit clock
24.576MHz master clock
INT4X is low, INT2X is high
However, the ZEROR and ZEROL pins are always low, indicating no data.
Now, Table II on page 8 indicates that 128xFs (24.576MHz here) is a supported MCLK frequency for Fs=192kHz. However, on page 3 it also says that MCLK period must be greater than 54ns (e.g. clock slower than 18MHz), except when using "Master Chip clock auto-divide feature." It also specifies that this period is for 256xFs mode, and doesn't speak to other multiples.
Before I start rerouting clocks, can anyone opine as to whether my MCLK is too high? I would guess that the "divide" feature is only for 512xFs and 768xFs, which means that at 128xFs my clock is too hot. Should I cut MCLK to 64xFs, 12.288MHz? I'm reluctant to do this when Table II clearly states that 128xFs is acceptable, but the behavior of the DAC looks to me like it isn't properly processing the input at all.
Here are all of the stupid mistakes I've thought to check for: I've measured the clocks and the SDATA line on the DAC pins, so I know these signals are being received, and that there is data on the SDATA line. I've triple checked the serial input format, although I would expect to get output even if this were wrong. I've used a reset generator to reset the chip (works fine with the other Analog IC on this board), and the ~RST line is high. Mute is low. Serial control pins are pulled low through 10K resistors. Supplies are nominal and grounds are connected. Oh, and my DIR is locked and outputting valid data.
I'm deeply in the debt of anyone who can offer some ideas. Thanks for looking!
I am not at all familiar with the 1853 but quickly checking the data sheet you seem to have got it right but then I remembered a query you had for me in another thread.......talking about generating clocks.
You do not explain where you get or how you create the master clock, I am thinking it might be out of sync in relation to the data and lr signals? If so the 1853 may just consider its getting unvalid data and shut off?
The master clock is syncronous, although I have info direct from Analog that says it doesn't actually have to be for this DAC. Thanks for the thought though...puzzling.
All three clocks are generated from a syncronous counter driven at 49.152MHz.
All three clocks are generated from a syncronous counter driven at 49.152MHz.
Tiroth,
Your theory work seems right on the money. It is clearly stated in the data sheet that that 128*fs is supported.
The auto divide circuitry sets up 32*fs internally.
When I did work on this chip a few years back (admittably I am not using 192KHz sampling rate - i.e not tested anyway), I did not have the problem that you describe. However, I did find the datasheet for the evaluation board invaluable as a "modifier" to the datasheet: EVAL1853eb http://www.analog.com/UploadedFiles/Evaluation_Boards/Tools/73140863EVAL1853EB_a.pdf
I am also curious how you generate the L/RCLK and SDATA. Have you tried hooking up another source with different frequencies just to verify that things work there? If you are using an input receiver such as that used on the evaluation board, please note that it does not typically support higher than 96KHz.
Petter
Your theory work seems right on the money. It is clearly stated in the data sheet that that 128*fs is supported.
The auto divide circuitry sets up 32*fs internally.
When I did work on this chip a few years back (admittably I am not using 192KHz sampling rate - i.e not tested anyway), I did not have the problem that you describe. However, I did find the datasheet for the evaluation board invaluable as a "modifier" to the datasheet: EVAL1853eb http://www.analog.com/UploadedFiles/Evaluation_Boards/Tools/73140863EVAL1853EB_a.pdf
I am also curious how you generate the L/RCLK and SDATA. Have you tried hooking up another source with different frequencies just to verify that things work there? If you are using an input receiver such as that used on the evaluation board, please note that it does not typically support higher than 96KHz.
Petter
I am pleased to say it is now working. I had a cold joint on pin 27 that measured fine but must have been intermittent in operation. Unfortunately I also changed MCLK to 12.288MHz, so I still have to go back and return it to 24.576MHz and verify that things still work.
The funny thing is that I called Analog and they were stumped about that period >= 54ns bit.
Thanks for the help!
The funny thing is that I called Analog and they were stumped about that period >= 54ns bit.
Thanks for the help!
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