Hi Bob
Precisely why I mentioned that source followers can have a low input impedance. At high frequencies, the parasitic capacitance can easily lead to parasitic oscillations. The point about "far out" is more to do whether your amplifier oscillates because of such effects ...
cheers
John
Precisely why I mentioned that source followers can have a low input impedance. At high frequencies, the parasitic capacitance can easily lead to parasitic oscillations. The point about "far out" is more to do whether your amplifier oscillates because of such effects ...
cheers
John
Bob Cordell said:
Thanks, Bob.
I think parts such as that APT MOSFET are best suited to applications requiring operation at low to moderate average dissipation, but high peak dissipation. That way getting the heat out of the device isn’t such an issue, but a reserve for handling very high, short duration transient currents can be retained.
A class G or class H public address amplifier sounds like a reasonable application, where high reliability and immunity to abuse are much more important factors than ultra-low THD.
Cheers,
Glen
What's the difference between IRF parts with and without suffix "N"?
For example IRFP250 and IRFP250N.
I can see some difference in the datasheet, C, Q, etc.
But what does this mean?
Is it IRFP250N is suited better for switching, while IRFP250 is for analog amps?
For example IRFP250 and IRFP250N.
I can see some difference in the datasheet, C, Q, etc.
But what does this mean?
Is it IRFP250N is suited better for switching, while IRFP250 is for analog amps?
john_ellis said:
Hello John,
I am not sure if you are the same writer of that article in Electronics World about Phase Lead and Input Lag (PLIL) compensation as an alternative to the usual miller cap - that you attributed to being first used in a Gemini amplifier apparently. Though I have never seen any schematics to this amp.
If you are _great_ article by the way!.
I have a few questions for you.....
If you look at Bob Cordell's amplifier in terms of the compensation schema (and I have seen others do this) he puts the lag comp. cap with resistor over the collectors of the differential pair and has the usual phase lead compensation albeit with an R added to this. The R component (from what I understand from your article) makes the phase lead compensation more likely to be further away from being stable than without it.
I read in an article by John linsley hood that adjusting the R with the phase lead cap helps make a perfect square wave with different load resistances and capacitances and also at high frequencies. Maybe with the addition of the lag comp. this is largely circumvented.
My questions are this 🙂
Do you think Bob's type (and others who have done this) of compensation gives lower THD compared with PLIL ? (negating error correction schemes for the time being) and do much for the input stage?
You showed a scope picture of the base to base voltage spikes when the input stage is overloaded with a miller type compensation versus a PLIL type scheme. I was wondering what your thoughts are about the compensation that Bob and I think other's like the Audiolab amps use. (over the collectors of the LTP)
would this still happen etc ?
Have you ever done comparisons (or got a feel) for whether Bob's approach gives lower THD than miller compensation or has disadvantages compared with a PLIL scheme ?
Pushing the envelope here (as usual) do you think it's possible to use dual pole compensation on the input lag part of using PLIL
compensation ?
I must admit I do quite like the advantages of dual pole compensation (if done right). PSRR, noise, THD etc are better at higher frequencies.
Some food for thought.
All the best
Kevin
Another question John!!
Do you know if the compensation scheme used by Bob in his error correction amp (let's ignore the Hawksford part of the circuit for the time being) has the same disadvantage as what JLH would do generating a lag over the base of the VAS transistor. ie. it does nothing for high frequency THD ?
Kev
Do you know if the compensation scheme used by Bob in his error correction amp (let's ignore the Hawksford part of the circuit for the time being) has the same disadvantage as what JLH would do generating a lag over the base of the VAS transistor. ie. it does nothing for high frequency THD ?
Kev
Mikeks, I would love you to join in.....and help me out here...
Anyway, I will be posting some scope pics to help clarify these matters.
Anyway, I will be posting some scope pics to help clarify these matters.
Here is a PLIL design. On the following page the designer recommends using anti saturation diodes and shows soft clipping.
Another approach to consider would be to place inductance
between the emitters of the diff pair, as patented by Deane
Jensen.
😎
between the emitters of the diff pair, as patented by Deane
Jensen.
😎
Fanuc said:
Here are a couple of things to keep in mind in regard to the compensation I used.
The lag compensation used above the differential pair is not part of the main compensation; it is secondary compensation that comes in at quite high frequencies to compensate the loop created by the main compenation.
Although I suppose some could view the compensation from the output of the VAS to the input of the diff pair as lead compensation, I don't think of it that way and don't design it that way. I think of it as analogous to Miller compensation that is just returned a stage earlier, thus enclosing the input stage in that local wideband loop and increasing its dynamic range. The resistor in series with the capacitor provides a stabilizing zero in the forward gain. View this all from the perspective of the output stage and you'll see what I mean.
Cheers,
Bob
Bob Cordell said:
Earlier on in this controversy 🙂 I thought it actually was lead compensation. Then I thought I'd try a sim, so I found and downloaded the sim from this post from jcx. Lo and behold, when I removed C4 and R13, the loop gain changed radically - not in the way one would expect from removing lead compensation. Then I became completely baffled as to how one would design the compensation. Just for grins, I increased the feedback resistors by a factor of 10. The unity loop gain freq decreased by a factor of 10! Then it hit me how it worked 🙂.
Bob Cordell said:
Could you pretty please articulate your design procedure for this type of compensation? Using your accessible 50W EC amp design as a reference would be good.
Cheers,
Glen
Oops, I just realized that the LTSpice sim of jcx that I quoted above didn't include the required model files for it to run. I've attached the model files below.
Glen, the trick is to take the Thevenin equivalent of the output voltage and feedback network, so the feedback network collapses to a single resistor. Then think of the path from the Thevenin equivalent of the output voltage to the VAS output as an op-amp integrator with an additional zero.
Glen, the trick is to take the Thevenin equivalent of the output voltage and feedback network, so the feedback network collapses to a single resistor. Then think of the path from the Thevenin equivalent of the output voltage to the VAS output as an op-amp integrator with an additional zero.
andy_c said:
G’day Andy.
The reason I asked the question is because in my attempts to optimise this form of compensation in spice simulation, I have found it impossible to eradicate high frequency peaking in the closed loop amplitude response.
The scheme works fine, so long as the output stage has a gain of exactly unity with zero output impedance. The problem, as far as I can tell, stems from the fact that there are two feedback paths, one from the VAS output and one from the power output, back to the inverting input of the diff amp. In a typical configuration, in which the input signal is applied to the non-inverting input of the diff amp, the inverting input is not a virtual ground; but both negative feedback paths have their characteristic defined by a shared resistor from this point to ground. This results in unavoidable interaction between the two feedback paths.
Simulate a frequency response plot of an amplifier using this compensation scheme, with a non-ideal output stage into a load to see what I mean.
Cheers,
Glen
G.Kleinschmidt said:
Hi Glen,
Here's how I do it. Let's assume I've chosen a closed loop gain of 20 and a gain crossover frequency of 2 MHz. This means that I want the forward gain of the combined input stage and VAS to be 20 at 1 MHz, assuming that the output stage has unity gain (if the output stage had a gain of 2, the target would be 10 instead). Having chosen the feedback shunt resistor to be 215 ohms, I now know that the reactance of C4 must be about 19 times 215 ohms at 1 MHz, or about 4k. Thus c4 becomes 20 pF.
I then want to put in a stabilizing zero at a frequency above the gain crossover frequency. This is done with R13 at 680 ohms. This gives me a zero at about 11 MHz.
Next I analyze and stabilize the inner loop that is closed by C4 and R13. This can be a high-bandwidth loop with a gain crossover beyond 10 MHz, since only small-signal fast transistors are in the loop. This fast loop is stabilized by C3 and R14. This is very light lag compensation.
Note that there is not a lot of interaction at the base of Q2 because the 215 ohm resistor is small compared to the impedances of C4 and R12.
The advantage of the scheme is that it rolls off the high frequency forward path gain by applying feedback around the input stage, increasing its dynamic range, reducing its distortion, and not making it work harder at high frequencies (the way Miller compensation does). It only has to work harder at very high frequencies where C3 comes in, but this is pretty far out.
This compensation approach is what allows me to get 300 V/us slew rate. It is like input compensation in a way, but is more elegant because it does not use the brute force of shunt lag compensation across the input gates.
Cheers,
Bob
AndrewT said:
Thanks. Probably a good idea. I started using it about 25 years ago when I did the MOSFET power amp with error correction. I honestly don't know where it came from. If anyone here has a pre-dating reference to the technique, I'd appreciate it. Did someone here say JLH used it or something very similar? I know I was fooling around with input compensation schemes at the time, and I suppose I could have come up with it as an evolution of input compensation, but I doubt it; I probably saw it or something similar someplace. I was designing linear integrated circuits at the time at Bell Labs and recall looking at compensation schemes in the LM318 and 5534 as well.
There is another advantage to this scheme. Conventional Miller compensation can degrade PSRR because one end of the Miller capacitor is referenced to signal while the other end (at the base of the VAS) is effectively referenced to the supply rail. In this scheme, both ends of the compensating capacitor are referenced to clean signal nodes.
Cheers,
Bob
Hi
---Conventional Miller compensation can degrade PSRR because one end of the Miller capacitor is referenced to signal while the other end (at the base of the VAS) is effectively referenced to the supply rail. In this scheme, both ends of the compensating capacitor are referenced to clean signal nodes.---
Is this Self's idea in the convetional scheme a good one : to connect the other end of the Miller capacitor to the emitter of a common base bipolar (base referenced to ground) in a cascode input stage ?
---Conventional Miller compensation can degrade PSRR because one end of the Miller capacitor is referenced to signal while the other end (at the base of the VAS) is effectively referenced to the supply rail. In this scheme, both ends of the compensating capacitor are referenced to clean signal nodes.---
Is this Self's idea in the convetional scheme a good one : to connect the other end of the Miller capacitor to the emitter of a common base bipolar (base referenced to ground) in a cascode input stage ?